| 8037285 |
Trace unit |
Richard Win Thaik, John G. Favor, Joseph B. Rowlands, Matthew William Ashcraft, Ivan Pavle Radivojevic |
2011-10-11 |
| 8032710 |
System and method for ensuring coherency in trace execution |
Matthew William Ashcraft, John G. Favor, Joseph B. Rowlands, Richard Win Thaik |
2011-10-04 |
| 8015359 |
Method and system for utilizing a common structure for trace verification and maintaining coherency in an instruction processing circuit |
John G. Favor, Joseph B. Rowlands, Richard Win Thaik |
2011-09-06 |
| 7987342 |
Trace unit with a decoder, a basic-block cache, a multi-block cache, and sequencer |
Richard Win Thaik, John G. Favor, Joseph B. Rowlands |
2011-07-26 |
| 7966479 |
Concurrent vs. low power branch prediction |
Richard Win Thaik, John G. Favor, Joseph B. Rowlands |
2011-06-21 |
| 7953933 |
Instruction cache, decoder circuit, basic block cache circuit and multi-block cache circuit |
Richard Win Thaik, John G. Favor, Joseph B. Rowlands |
2011-05-31 |
| 7953961 |
Trace unit with an op path from a decoder (bypass mode) and from a basic-block builder |
Richard Win Thaik, John G. Favor, Joseph B. Rowlands |
2011-05-31 |
| 7949854 |
Trace unit with a trace builder |
Richard Win Thaik, John G. Favor, Joseph B. Rowlands |
2011-05-24 |
| 7941607 |
Method and system for promoting traces in an instruction processing circuit |
Richard Win Thaik, John G. Favor, Joseph B. Rowlands, Matthew William Ashcraft |
2011-05-10 |
| 7814298 |
Promoting and appending traces in an instruction processing circuit based upon a bias value |
Richard Win Thaik, John G. Favor, Joseph B. Rowlands, Matthew William Ashcraft |
2010-10-12 |
| 7676634 |
Selective trace cache invalidation for self-modifying code via memory aging |
Kevin Paul Lawton |
2010-03-09 |
| 7606975 |
Trace cache for efficient self-modifying code processing |
Kevin Paul Lawton |
2009-10-20 |
| 7546420 |
Efficient trace cache management during self-modifying code processing |
Kevin Paul Lawton |
2009-06-09 |
