RT

Richard Win Thaik

Oracle: 17 patents #564 of 14,854Top 4%
NS National Semiconductor: 2 patents #867 of 2,238Top 40%
NS Negotiated Data Solutions: 2 patents #3 of 8Top 40%
AC Ampere Computing: 1 patents #52 of 94Top 60%
MS Macom Connectivity Solutions: 1 patents #11 of 27Top 45%
Overall (All Time): #183,285 of 4,157,543Top 5%
23
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11093401 Hazard prediction for a group of memory access instructions using a buffer associated with branch prediction Matthew William Ashcraft 2021-08-17
9880849 Allocation of load instruction(s) to a queue buffer in a processor system based on prediction of an instruction pipeline hazard Matthew William Ashcraft 2018-01-30
8499293 Symbolic renaming optimization of a trace Matthew William Ashcraft, John G. Favor, Christopher Patrick Nelson, Ivan Pavle Radivojevic, Joseph B. Rowlands 2013-07-30
8037285 Trace unit John G. Favor, Joseph B. Rowlands, Leonard Eric Shar, Matthew William Ashcraft, Ivan Pavle Radivojevic 2011-10-11
8032710 System and method for ensuring coherency in trace execution Matthew William Ashcraft, John G. Favor, Joseph B. Rowlands, Leonard Eric Shar 2011-10-04
8015359 Method and system for utilizing a common structure for trace verification and maintaining coherency in an instruction processing circuit John G. Favor, Joseph B. Rowlands, Leonard Eric Shar 2011-09-06
7987342 Trace unit with a decoder, a basic-block cache, a multi-block cache, and sequencer John G. Favor, Joseph B. Rowlands, Leonard Eric Shar 2011-07-26
7966479 Concurrent vs. low power branch prediction John G. Favor, Joseph B. Rowlands, Leonard Eric Shar 2011-06-21
7953933 Instruction cache, decoder circuit, basic block cache circuit and multi-block cache circuit John G. Favor, Joseph B. Rowlands, Leonard Eric Shar 2011-05-31
7953961 Trace unit with an op path from a decoder (bypass mode) and from a basic-block builder John G. Favor, Joseph B. Rowlands, Leonard Eric Shar 2011-05-31
7949854 Trace unit with a trace builder John G. Favor, Joseph B. Rowlands, Leonard Eric Shar 2011-05-24
7941607 Method and system for promoting traces in an instruction processing circuit John G. Favor, Joseph B. Rowlands, Leonard Eric Shar, Matthew William Ashcraft 2011-05-10
7937564 Emit vector optimization of a trace Matthew William Ashcraft, John G. Favor, Christopher Patrick Nelson, Ivan Pavle Radivojevic, Joseph B. Rowlands 2011-05-03
7870369 Abort prioritization in a trace-based processor Christopher Patrick Nelson, John G. Favor 2011-01-11
7849292 Flag optimization of a trace Matthew William Ashcraft, John G. Favor, Christopher Patrick Nelson, Ivan Pavle Radivojevic, Joseph B. Rowlands 2010-12-07
7814298 Promoting and appending traces in an instruction processing circuit based upon a bias value John G. Favor, Joseph B. Rowlands, Leonard Eric Shar, Matthew William Ashcraft 2010-10-12
7783863 Graceful degradation in a trace-based processor Christopher Patrick Nelson, John G. Favor, Matthew William Ashcraft 2010-08-24
7747822 Maintaining memory coherency with a trace cache John G. Favor 2010-06-29
7673122 Software hint to specify the preferred branch prediction to use for a branch instruction Seungyoon Peter Song, John G. Favor 2010-03-02
RE39395 Data communication network with transfer port, cascade port and/or frame synchronizing signal Geetha N. K. Rangan, Debra J. Worsley, Brian C. Edem 2006-11-14
RE39216 Asynchronous processor access to a switch table in a network with isochronous capability Debra J. Worsley, Michael T. Werstlein 2006-08-01
5594734 Asynchronous processor access to a switch table in a network with isochronous capability Debra J. Worsley, Michael T. Werstlein 1997-01-14
5566169 Data communication network with transfer port, cascade port and/or frame synchronizing signal Geetha N. K. Rangan, Debra J. Worsley, Brian C. Edem 1996-10-15