| 11513798 |
Implementation of load acquire/store release instructions using load/store operation with DMB operation |
Matthew William Ashcraft |
2022-11-29 |
| 8499293 |
Symbolic renaming optimization of a trace |
Matthew William Ashcraft, John G. Favor, Ivan Pavle Radivojevic, Joseph B. Rowlands, Richard Win Thaik |
2013-07-30 |
| 7937564 |
Emit vector optimization of a trace |
Matthew William Ashcraft, John G. Favor, Ivan Pavle Radivojevic, Joseph B. Rowlands, Richard Win Thaik |
2011-05-03 |
| 7870369 |
Abort prioritization in a trace-based processor |
John G. Favor, Richard Win Thaik |
2011-01-11 |
| 7849292 |
Flag optimization of a trace |
Matthew William Ashcraft, John G. Favor, Ivan Pavle Radivojevic, Joseph B. Rowlands, Richard Win Thaik |
2010-12-07 |
| 7783863 |
Graceful degradation in a trace-based processor |
John G. Favor, Richard Win Thaik, Matthew William Ashcraft |
2010-08-24 |
| 7587585 |
Flag management in processors enabled for speculative execution of micro-operation traces |
John G. Favor, Seungyoon Peter Song |
2009-09-08 |
| 7568088 |
Flag management in processors enabled for speculative execution of micro-operation traces |
John G. Favor, Seungyoon Peter Song |
2009-07-28 |
| 7568089 |
Flag management in processors enabled for speculative execution of micro-operation traces |
John G. Favor, Seungyoon Peter Song |
2009-07-28 |
| 7493471 |
Coprocessor receiving renamed register identifier from master to complete an operation upon register data ready |
John G. Favor |
2009-02-17 |
| 7490223 |
Dynamic resource allocation among master processors that require service from a coprocessor |
John G. Favor |
2009-02-10 |
| 7490225 |
Synchronizing master processor by stalling when tracking of coprocessor rename register resource usage count for sent instructions reaches credited apportioned number |
John G. Favor |
2009-02-10 |
| 7389408 |
Microarchitecture for compact storage of embedded constants |
John G. Favor |
2008-06-17 |
