| 7263600 |
System and method for validating a memory file that links speculative results of load operations to register values |
Benjamin T. Sander, Krishnan V. Ramani, Mitchell Alsup |
2007-08-28 |
| 6889312 |
Selective zero extension based on operand size |
Kevin J. McGrath, Bruce R. Holloway, I-Cheng Chen |
2005-05-03 |
| 6807616 |
Memory address checking in a proccesor that support both a segmented and a unsegmented address space |
Kevin J. McGrath, Chetana N. Keltcher |
2004-10-19 |
| 6694424 |
Store load forward predictor training |
James B. Keller, Thomas S. Green, Wei-Han Lien |
2004-02-17 |
| 6651161 |
Store load forward predictor untraining |
James B. Keller, Thomas S. Green, Wei-Han Lien |
2003-11-18 |
| 6622235 |
Scheduler which retries load/store hit situations |
James B. Keller, Stephan G. Meier |
2003-09-16 |
| 6622237 |
Store to load forward predictor training using delta tag |
James B. Keller, Thomas S. Green, Wei-Han Lien, Keith R. Schakel |
2003-09-16 |
| 6564315 |
Scheduler which discovers non-speculative nature of an instruction after issuing and reissues the instruction |
James B. Keller, Stephan G. Meier |
2003-05-13 |
| 6542984 |
Scheduler capable of issuing and reissuing dependency chains |
James B. Keller, Stephan G. Meier |
2003-04-01 |
| 6481251 |
Store queue number assignment and tracking |
Stephan G. Meier |
2002-11-19 |
| 6363471 |
Mechanism for handling 16-bit addressing in a processor |
Stephan G. Meier, Bruce Gieseke, William McGee |
2002-03-26 |
| 5787465 |
Destination indexed miss status holding registers |
Norman Paul Jouppi |
1998-07-28 |