Issued Patents All Time
Showing 76–100 of 120 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6625685 | Memory controller with programmable configuration | James Y. Cho, Mark D. Hayter | 2003-09-23 |
| 6622235 | Scheduler which retries load/store hit situations | Ramsey W. Haddad, Stephan G. Meier | 2003-09-16 |
| 6622237 | Store to load forward predictor training using delta tag | Thomas S. Green, Wei-Han Lien, Ramsey W. Haddad, Keith R. Schakel | 2003-09-16 |
| 6564315 | Scheduler which discovers non-speculative nature of an instruction after issuing and reissues the instruction | Ramsey W. Haddad, Stephan G. Meier | 2003-05-13 |
| 6560694 | Double prefix overrides to provide 16-bit operand size in a 32/64 operating mode | Kevin J. McGrath | 2003-05-06 |
| 6557048 | Computer system implementing a system and method for ordering input/output (IO) memory operations within a coherent portion thereof | Derrick R. Meyer, Dale E. Gulick, Larry D. Hewitt | 2003-04-29 |
| 6553430 | Computer system implementing flush operation | — | 2003-04-22 |
| 6546478 | Line predictor entry with location pointers and control information for corresponding instructions in a cache line | Puneet Sharma, Keith R. Schakel, Francis Matus | 2003-04-08 |
| 6542984 | Scheduler capable of issuing and reissuing dependency chains | Ramsey W. Haddad, Stephan G. Meier | 2003-04-01 |
| 6529999 | Computer system implementing system and method for ordering write operations and maintaining memory coherency | Derrick R. Meyer | 2003-03-04 |
| 6502185 | Pipeline elements which verify predecode information | Puneet Sharma, Keith R. Schakel, Francis Matus | 2002-12-31 |
| 6493802 | Method and apparatus for performing speculative memory fills into a microprocessor | Rahul Razdan, Richard E. Kessler | 2002-12-10 |
| 6490661 | Maintaining cache coherency during a memory read operation in a multiprocessing computer system | Derrick R. Meyer | 2002-12-03 |
| 6473849 | Implementing locks in a distributed processing system | William A. Hughes | 2002-10-29 |
| 6434640 | Unload counter adjust logic for a receiver buffer | — | 2002-08-13 |
| 6401173 | Method and apparatus for optimizing bcache tag performance by inferring bcache tag state from internal processor state | Rahul Razdan, David A. Webb | 2002-06-04 |
| 6397302 | Method and apparatus for developing multiprocessor cache control protocols by presenting a clean victim signal to an external system | Rahul Razdan, Richard E. Kessler | 2002-05-28 |
| 6393546 | Physical rename register for efficiently storing floating point, integer, condition code, and multimedia values | David B. Witt | 2002-05-21 |
| 6393529 | Conversation of distributed memory bandwidth in multiprocessor system with cache coherency by transmitting cancel subsequent to victim write | — | 2002-05-21 |
| 6389526 | Circuit and method for selectively stalling interrupt requests initiated by devices coupled to a multiprocessor system | Dale E. Gulick, Larry D. Hewitt, Geoffrey S. Strongin | 2002-05-14 |
| 6385705 | Circuit and method for maintaining order of memory access requests initiated by devices in a multiprocessor system | Dale E. Gulick, Larry D. Hewitt, Geoffrey S. Strongin | 2002-05-07 |
| 6374344 | Methods and apparatus for processing load instructions in the presence of RAM array and data bus conflicts | David A. Webb, Derrick R. Meyer | 2002-04-16 |
| 6370621 | Memory cancel response optionally cancelling memory controller's providing of data in response to a read operation | — | 2002-04-09 |
| 6360314 | Data cache having store queue bypass for out-of-order instruction execution and method for same | David A. Webb, Derrick R. Meyer | 2002-03-19 |
| 6349366 | Method and apparatus for developing multiprocessor cache control protocols using a memory management system generating atomic probe commands and system data control response commands | Rahul Razdan, Richard E. Kessler | 2002-02-19 |