Issued Patents All Time
Showing 101–120 of 120 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6314496 | Method and apparatus for developing multiprocessor cache control protocols using atomic probe commands and system data control response commands | Rahul Razdan, Richard E. Kessler | 2001-11-06 |
| 6295583 | Method and apparatus for resolving probes in multi-processor systems which do not use external duplicate tags for probe filtering | Rahul Razdan, Solomon J. Katzman, Richard E. Kessler | 2001-09-25 |
| 6275905 | Messaging scheme to maintain cache coherency and conserve system memory bandwidth during a memory read operation in a multiprocessing computer system | Derrick R. Meyer | 2001-08-14 |
| 6266763 | Physical rename register for efficiently storing floating point, integer, condition code, and multimedia values | David B. Witt | 2001-07-24 |
| 6253301 | Method and apparatus for a dedicated physically indexed copy of the data cache tag arrays | Rahul Razdan, David A. Webb, Derrick R. Meyer | 2001-06-26 |
| 6253285 | Method and apparatus for minimizing dcache index match aliasing using hashing in synonym/subset processing | Rahul Razdan, Richard E. Kessler | 2001-06-26 |
| 6212493 | Profile directed simulation used to target time-critical crossproducts during random vector testing | James D. Huggins, David Asher | 2001-04-03 |
| 6199153 | Method and apparatus for minimizing pincount needed by external memory control chip for multiprocessors with limited memory size requirements | Rahul Razdan, Solomon J. Katzman, Richard E. Kessler | 2001-03-06 |
| 6167492 | Circuit and method for maintaining order of memory access requests initiated by devices coupled to a multiprocessor system | Dale E. Gulick, Larry D. Hewitt, Geoffrey S. Strongin | 2000-12-26 |
| 6163821 | Method and apparatus for balancing load vs. store access to a primary data cache | Richard E. Kessler, Stephen C. Root, Paul Geoffrey Lowney | 2000-12-19 |
| 6141734 | Method and apparatus for optimizing the performance of LDxL and STxC interlock instructions in the context of a write invalidate protocol | Rahul Razdan, David A. Webb, Derrick R. Meyer, Daniel Leibholz | 2000-10-31 |
| 6101581 | Separate victim buffer read and release control | Stephen Doren, Simon C. Steely, Jr., Robert Eugene Stewart | 2000-08-08 |
| 6061765 | Independent victim data buffer and probe buffer release control utilzing control flag | Stephen R. Van Doren, Simon C. Steely, Jr., Robert Eugene Stewart | 2000-05-09 |
| 5924120 | Method and apparatus for maximizing utilization of an internal processor bus in the context of external transactions running at speeds fractionally greater than internal transaction times | Rahul Razdan, David A. Webb, Derrick R. Meyer | 1999-07-13 |
| 5202973 | Method of controlling a shared memory bus in a multiprocessor system for preventing bus collisions and for ensuring a full bus | Raj K. Ramanujan, Jay C. Stickney, Steven Ho, Paul J. Lemmon | 1993-04-13 |
| 5029076 | Apparatus and method for providing a settling time cycle for a system bus in a data processing system | Robert E. Stewart | 1991-07-02 |
| 5012403 | Apparatus and method for replaying decoded instructions | Kevin L. Ladd, James J. Reisert | 1991-04-30 |
| 4878193 | Method and apparatus for accelerated addition of sliced addends | Debra Bernstein | 1989-10-31 |
| 4858173 | Apparatus and method for responding to an aborted signal exchange between subsystems in a data processing system | Robert E. Stewart, Paul J. Natusch, Eugene L. Yu | 1989-08-15 |
| 4755936 | Apparatus and method for providing a cache memory unit with a write operation utilizing two system clock cycles | Robert E. Stewart, Barry J. Flahive | 1988-07-05 |