David B. Witt — 107 Patents at AMD

David B. Witt has been granted 107 US patents while listed as an inventor at AMD. The first was granted in 1988 and the most recent in November 2024. David B. Witt ranks #12,671 of 4,157,543 US inventors in our database (top 0.30%). Patent records list David B. Witt in Austin, TX, US.

Issued Patents All Time

Showing 1–25 of 107 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
12141580	Microprocessor with non-cacheable memory load prediction	Thang M. Tran	2024-11-12
7120781	General purpose register file architecture for aligned simd	Ravi Kolagotla, Bradley C. Aldrich	2006-10-10
6918028	Pipelined processor including a loosely coupled side pipe	—	2005-07-12	$30,576,000
6584556	Modulo address generation method and apparatus	—	2003-06-24	$76,286,000
6553482	Universal dependency vector/queue entry	—	2003-04-22	$3,266,000
6505292	Processor including efficient fetch mechanism for L0 and L1 caches	—	2003-01-07	$3,897,000
6457117	Processor configured to predecode relative control transfer instructions and replace displacements therein with a target address	—	2002-09-24	$1,057,000
6446181	System having a configurable cache/SRAM memory	Hebbalalu S. Ramagopal, Michael S. Allen, Moinul Syed, Ravi Kolagotla, Lawrence A. Booth, Jr. +1 more	2002-09-03
6404324	Resistive component for use with short duration, high-magnitude currents	Scott E. Crawford	2002-06-11
6393549	Instruction alignment unit for routing variable byte-length instructions	Thang M. Tran	2002-05-21	$2,063,000
6393546	Physical rename register for efficiently storing floating point, integer, condition code, and multimedia values	James B. Keller	2002-05-21	$2,063,000
6381689	Line-oriented reorder buffer configured to selectively store a memory operation result in one of the plurality of reorder buffer storage locations corresponding to the executed instruction	Thang M. Tran	2002-04-30	$1,930,000
6367001	Processor including efficient fetch mechanism for L0 and L1 caches	—	2002-04-02	$3,760,000
6347369	Method and circuit for single cycle multiple branch history table access	—	2002-02-12	$7,726,000
6332191	System for canceling speculatively fetched instructions following a branch mis-prediction in a microprocessor	—	2001-12-18	$8,747,000
6332187	Cumulative lookahead to eliminate chained dependencies	—	2001-12-18	$8,747,000
6321326	Prefetch instruction specifying destination functional unit and read/write access mode	—	2001-11-20	$3,380,000
6308259	Instruction queue evaluating dependency vector in portions during different clock phases	—	2001-10-23	$2,669,000
6298423	High performance load/store functional unit and data cache	William M. Johnson, Murali Chinnakonda	2001-10-02	$2,425,000
6292884	Reorder buffer employing last in line indication	Thang M. Tran	2001-09-18	$2,710,000
6279101	Instruction decoder/dispatch	William M. Johnson	2001-08-21	$5,111,000
6266752	Reverse TLB for providing branch target address in a microprocessor having a physically-tagged cache	Thang M. Tran	2001-07-24	$3,903,000
6266763	Physical rename register for efficiently storing floating point, integer, condition code, and multimedia values	James B. Keller	2001-07-24	$3,903,000
6256728	Processor configured to selectively cancel instructions from its pipeline responsive to a predicted-taken short forward branch instruction	William M. Johnson	2001-07-03	$7,468,000
6256721	Register renaming in which moves are accomplished by swapping tags	—	2001-07-03	$7,468,000

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David B. Witt — 107 Patents

Issued Patents All Time

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