Issued Patents All Time
Showing 25 most recent of 107 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12141580 | Microprocessor with non-cacheable memory load prediction | Thang M. Tran | 2024-11-12 |
| 7120781 | General purpose register file architecture for aligned simd | Ravi Kolagotla, Bradley C. Aldrich | 2006-10-10 |
| 6918028 | Pipelined processor including a loosely coupled side pipe | — | 2005-07-12 |
| 6584556 | Modulo address generation method and apparatus | — | 2003-06-24 |
| 6553482 | Universal dependency vector/queue entry | — | 2003-04-22 |
| 6505292 | Processor including efficient fetch mechanism for L0 and L1 caches | — | 2003-01-07 |
| 6457117 | Processor configured to predecode relative control transfer instructions and replace displacements therein with a target address | — | 2002-09-24 |
| 6446181 | System having a configurable cache/SRAM memory | Hebbalalu S. Ramagopal, Michael S. Allen, Moinul Syed, Ravi Kolagotla, Lawrence A. Booth, Jr. +1 more | 2002-09-03 |
| 6404324 | Resistive component for use with short duration, high-magnitude currents | Scott E. Crawford | 2002-06-11 |
| 6393549 | Instruction alignment unit for routing variable byte-length instructions | Thang M. Tran | 2002-05-21 |
| 6393546 | Physical rename register for efficiently storing floating point, integer, condition code, and multimedia values | James B. Keller | 2002-05-21 |
| 6381689 | Line-oriented reorder buffer configured to selectively store a memory operation result in one of the plurality of reorder buffer storage locations corresponding to the executed instruction | Thang M. Tran | 2002-04-30 |
| 6367001 | Processor including efficient fetch mechanism for L0 and L1 caches | — | 2002-04-02 |
| 6347369 | Method and circuit for single cycle multiple branch history table access | — | 2002-02-12 |
| 6332187 | Cumulative lookahead to eliminate chained dependencies | — | 2001-12-18 |
| 6332191 | System for canceling speculatively fetched instructions following a branch mis-prediction in a microprocessor | — | 2001-12-18 |
| 6321326 | Prefetch instruction specifying destination functional unit and read/write access mode | — | 2001-11-20 |
| 6308259 | Instruction queue evaluating dependency vector in portions during different clock phases | — | 2001-10-23 |
| 6298423 | High performance load/store functional unit and data cache | William M. Johnson, Murali Chinnakonda | 2001-10-02 |
| 6292884 | Reorder buffer employing last in line indication | Thang M. Tran | 2001-09-18 |
| 6279101 | Instruction decoder/dispatch | William M. Johnson | 2001-08-21 |
| 6266752 | Reverse TLB for providing branch target address in a microprocessor having a physically-tagged cache | Thang M. Tran | 2001-07-24 |
| 6266763 | Physical rename register for efficiently storing floating point, integer, condition code, and multimedia values | James B. Keller | 2001-07-24 |
| 6256728 | Processor configured to selectively cancel instructions from its pipeline responsive to a predicted-taken short forward branch instruction | William M. Johnson | 2001-07-03 |
| 6256721 | Register renaming in which moves are accomplished by swapping tags | — | 2001-07-03 |