Issued Patents All Time
Showing 51–75 of 107 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6088789 | Prefetch instruction specifying destination functional unit and read/write access mode | — | 2000-07-11 |
| 6081656 | Method for deriving a double frequency microprocessor from an existing microprocessor | — | 2000-06-27 |
| 6079003 | Reverse TLB for providing branch target address in a microprocessor having a physically-tagged cache | Thang M. Tran | 2000-06-20 |
| 6079005 | Microprocessor including virtual address branch prediction and current page register to provide page portion of virtual and physical fetch address | Thang M. Tran | 2000-06-20 |
| 6061786 | Processor configured to select a next fetch address by partially decoding a byte of a control transfer instruction | — | 2000-05-09 |
| 6032251 | Computer system including a microprocessor having a reorder buffer employing last in buffer and last in line indications | Thang M. Tran | 2000-02-29 |
| 6026482 | Recorder buffer and a method for allocating a fixed amount of storage for instruction results independent of a number of concurrently dispatched instructions | Thang M. Tran | 2000-02-15 |
| 6018798 | Floating point unit using a central window for storing instructions capable of executing multiple instructions in a single clock cycle | Derrick R. Meyer | 2000-01-25 |
| 6006324 | High performance superscalar alignment unit | Thang M. Tran | 1999-12-21 |
| 5991869 | Superscalar microprocessor including a high speed instruction alignment unit | Thang M. Tran, William M. Johnson | 1999-11-23 |
| 5987561 | Superscalar microprocessor employing a data cache capable of performing store accesses in a single clock cycle | Rajiv M. Hattangadi | 1999-11-16 |
| 5978907 | Delayed update register for an array | Thang M. Tran | 1999-11-02 |
| 5970235 | Pre-decoded instruction cache and method therefor particularly suitable for variable byte-length instructions | Michael D. Goddard | 1999-10-19 |
| 5946468 | Reorder buffer having an improved future file for storing speculative instruction execution results | Thang M. Tran | 1999-08-31 |
| 5944815 | Microprocessor configured to execute a prefetch instruction including an access count field defining an expected number of access | — | 1999-08-31 |
| 5915110 | Branch misprediction recovery in a reorder buffer having a future file | Thang M. Tran | 1999-06-22 |
| 5903910 | Method for transferring data between a pair of caches configured to be accessed from different stages of an instruction processing pipeline | Thang M. Tran, Marty Pflum, William M. Johnson | 1999-05-11 |
| 5903741 | Method of allocating a fixed reorder buffer storage line for execution results regardless of a number of concurrently dispatched instructions | Thang M. Tran | 1999-05-11 |
| 5901302 | Superscalar microprocessor having symmetrical, fixed issue positions each configured to execute a particular subset of instructions | Thang M. Tran | 1999-05-04 |
| 5878255 | Update unit for providing a delayed update to a branch prediction array | Thang M. Tran | 1999-03-02 |
| 5878245 | High performance load/store functional unit and data cache | William M. Johnson, Murali Chinnakonda | 1999-03-02 |
| 5878244 | Reorder buffer configured to allocate storage capable of storing results corresponding to a maximum number of concurrently receivable instructions regardless of a number of instructions received | Thang M. Tran | 1999-03-02 |
| 5875324 | Superscalar microprocessor which delays update of branch prediction information in response to branch misprediction until a subsequent idle clock | Thang M. Tran | 1999-02-23 |
| 5867683 | Method of operating a high performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations | William M. Johnson | 1999-02-02 |
| 5867682 | High performance superscalar microprocessor including a circuit for converting CISC instructions to RISC operations | William M. Johnson | 1999-02-02 |