Issued Patents All Time
Showing 76–100 of 107 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5860104 | Data cache which speculatively updates a predicted data cache storage location with store data and subsequently corrects mispredicted updates | Rajiv M. Hattangadi | 1999-01-12 |
| 5848287 | Superscalar microprocessor including a reorder buffer which detects dependencies between accesses to a pair of caches | Thang M. Tran, William M. Johnson | 1998-12-08 |
| 5835753 | Microprocessor with dynamically extendable pipeline stages and a classifying circuit | — | 1998-11-10 |
| 5835744 | Microprocessor configured to swap operands in order to minimize dependency checking logic | Thang M. Tran, William M. Johnson | 1998-11-10 |
| 5832249 | High performance superscalar alignment unit | Thang M. Tran | 1998-11-03 |
| 5831462 | Conditional latching mechanism and pipelined microprocessor employing the same | Marty Pflum | 1998-11-03 |
| 5828869 | Microprocessor arranged for synchronously accessing an external memory with a scalable clocking mechanism | William M. Johnson | 1998-10-27 |
| 5826053 | Speculative instruction queue and method therefor particularly suitable for variable byte-length instructions | — | 1998-10-20 |
| 5819057 | Superscalar microprocessor including an instruction alignment unit with limited dispatch to decode units | Thang M. Tran | 1998-10-06 |
| 5813045 | Conditional early data address generation mechanism for a microprocessor | Rupaka Mahalingaiah, Thang M. Tran | 1998-09-22 |
| 5805912 | Microprocessor arranged to synchronously access an external memory operating at a slower rate than the microproccessor | William M. Johnson | 1998-09-08 |
| 5796973 | Method and apparatus for decoding one or more complex instructions into concurrently dispatched simple instructions | Michael D. Goddard | 1998-08-18 |
| 5768555 | Reorder buffer employing last in buffer and last in line bits | Thang M. Tran | 1998-06-16 |
| 5761691 | Linearly addressable microprocessor cache | — | 1998-06-02 |
| 5758114 | High speed instruction alignment unit for aligning variable byte-length instructions according to predecode information in a superscalar microprocessor | William M. Johnson, Thang M. Tran | 1998-05-26 |
| 5751981 | High performance superscalar microprocessor including a speculative instruction queue for byte-aligning CISC instructions stored in a variable byte-length format | William M. Johnson | 1998-05-12 |
| 5689672 | Pre-decoded instruction cache and method therefor particularly suitable for variable byte-length instructions | Michael D. Goddard | 1997-11-18 |
| 5684422 | Pipelined microprocessor including a high speed single-clock latch circuit | Marty Pflum | 1997-11-04 |
| 5664136 | High performance superscalar microprocessor including a dual-pathway circuit for converting cisc instructions to risc operations | William M. Johnson | 1997-09-02 |
| 5655097 | High performance superscalar microprocessor including an instruction cache circuit for byte-aligning CISC instructions stored in a variable byte-length format | William M. Johnson | 1997-08-05 |
| 5655098 | High performance superscalar microprocessor including a circuit for byte-aligning cisc instructions stored in a variable byte-length format | William M. Johnson | 1997-08-05 |
| 5651125 | High performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations | William M. Johnson | 1997-07-22 |
| 5630100 | Simulating multi-phase clock designs using a single clock edge based system | Gopi Ganapathy | 1997-05-13 |
| 5623627 | Computer memory architecture including a replacement cache | — | 1997-04-22 |
| 5623619 | Linearly addressable microprocessor cache | — | 1997-04-22 |