Issued Patents All Time
Showing 26–50 of 107 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6247106 | Processor configured to map logical register numbers to physical register numbers using virtual register numbers | — | 2001-06-12 |
| 6240484 | Linearly addressable microprocessor cache | — | 2001-05-29 |
| 6240503 | Cumulative lookahead to eliminate chained dependencies | — | 2001-05-29 |
| 6237082 | Reorder buffer configured to allocate storage for instruction results corresponding to predefined maximum number of concurrently receivable instructions independent of a number of instructions received | Thang M. Tran | 2001-05-22 |
| 6230262 | Processor configured to selectively free physical registers upon retirement of instructions | — | 2001-05-08 |
| 6219784 | Processor with N adders for parallel target addresses calculation | — | 2001-04-17 |
| 6212622 | Mechanism for load block on store address generation | — | 2001-04-03 |
| 6212623 | Universal dependency vector/queue entry | — | 2001-04-03 |
| 6202139 | Pipelined data cache with multiple ports and processor with load/store unit selecting only load or store operations for concurrent processing | James K. Pickett | 2001-03-13 |
| 6199154 | Selecting cache to fetch in multi-level cache system based on fetch address source and pre-fetching additional data to the cache for future access | — | 2001-03-06 |
| 6192462 | Superscalar microprocessor including a load/store unit, decode units and a reorder buffer to detect dependencies between access to a stack cache and a data cache | Thang M. Tran, William M. Johnson | 2001-02-20 |
| 6189068 | Superscalar microprocessor employing a data cache capable of performing store accesses in a single clock cycle | Rajiv M. Hattangadi | 2001-02-13 |
| 6189087 | Superscalar instruction decoder including an instruction queue | Michael D. Goddard | 2001-02-13 |
| 6167506 | Replacing displacement in control transfer instruction with encoding indicative of target address, including offset and target cache line location | — | 2000-12-26 |
| 6161167 | Fully associate cache employing LRU groups for cache replacement and mechanism for selecting an LRU group | — | 2000-12-12 |
| 6157986 | Fast linear tag validation unit for use in microprocessor | — | 2000-12-05 |
| 6141747 | System for store to load forwarding of individual bytes from separate store buffer entries to form a single load word | — | 2000-10-31 |
| 6134651 | Reorder buffer employed in a microprocessor to store instruction results having a plurality of entries predetermined to correspond to a plurality of functional units | Thang M. Tran | 2000-10-17 |
| 6134649 | Control transfer indication in predecode which identifies control transfer instruction and an alternate feature of an instruction | — | 2000-10-17 |
| 6122656 | Processor configured to map logical register numbers to physical register numbers using virtual register numbers | — | 2000-09-19 |
| 6122727 | Symmetrical instructions queue for high clock frequency scheduling | — | 2000-09-19 |
| 6119223 | Map unit having rapid misprediction recovery | — | 2000-09-12 |
| 6112296 | Floating point stack manipulation using a register map and speculative top of stack values | Derrick R. Meyer | 2000-08-29 |
| 6112293 | Processor configured to generate lookahead results from operand collapse unit and for inhibiting receipt/execution of the first instruction based on the lookahead result | — | 2000-08-29 |
| 6094716 | Register renaming in which moves are accomplished by swapping rename tags | — | 2000-07-25 |