Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5721695 | Simulation by emulating level sensitive latches with edge trigger latches | Brian D. McMinn | 1998-02-24 |
| 5630100 | Simulating multi-phase clock designs using a single clock edge based system | David B. Witt | 1997-05-13 |
| 5561792 | Microprocessor with software switchable clock speed and drive strength | — | 1996-10-01 |
| 5502414 | Circuit for delaying data latching from a precharged bus and method | Thang M. Tran, Michael D. Goddard, Robert C. Thaden | 1996-03-26 |
| 5450418 | Pseudo master slave capture mechanism for scan elements | — | 1995-09-12 |
| 5444407 | Microprocessor with distributed clock generators | Stephen C. Horne | 1995-08-22 |
| 5426650 | Full scan optimization technique using drive one/drive zero elements and multiple capture clocking | Robert C. Thaden, Steve Horne | 1995-06-20 |
| 5412663 | Apparatus for synchronizing asynchronous circuits for testing operations | Stephen C. Kromer | 1995-05-02 |