Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5721953 | Interface for logic simulation using parallel bus for concurrent transfers and having FIFO buffers for sending data to receiving units when ready | Mark Sweet | 1998-02-24 |
| 5548785 | Interface for logic simulation using parallel bus for concurrent transfers and having fifo buffers for sending data to receiving units when ready | Mark Sweet | 1996-08-20 |
| 5301302 | Memory mapping and special write detection in a system and method for simulating a CPU processor | Joe Wayne Blackard, Arturo M. de Nicolas | 1994-04-05 |
| 5251303 | System for DMA block data transfer based on linked control blocks | Joseph R. Mathis, James O. Nicholson | 1993-10-05 |
| 5129064 | System and method for simulating the I/O of a processing system | Arturo M. de Nicholas, John C. O'Quin, III | 1992-07-07 |
| 5008816 | Data processing system with multi-access memory | John W. Irwin | 1991-04-16 |
| 4995056 | System and method for data communications | Joseph R. Mathis, Carl Zeitler | 1991-02-19 |
| 4951195 | Condition code graph analysis for simulating a CPU processor | Arturo M. de Nicolas | 1990-08-21 |