Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9626243 | Data error correction device and methods thereof | — | 2017-04-18 |
| 9306694 | Clock signal synchronization among computers in a network | Daniel N. de Araujo, James T. Hanna, Bruce J. Wilkie | 2016-04-05 |
| 8199695 | Clock signal synchronization among computers in a network | Daniel N. de Araujo, James T. Hanna, Bruce J. Wilkie | 2012-06-12 |
| 6807232 | System and method for multiplexing synchronous digital data streams | Charles G. Schroeder, Brian Johnson | 2004-10-19 |
| 6226720 | Method for optimally configuring memory in a mixed interleave system | Daniel James Henderson, John Hughes Rost | 2001-05-01 |
| 6223299 | Enhanced error handling for I/O load/store operations to a PCI device via bad parity or zero byte enables | Douglas Craig Bossen, Charles Andrew McLaughlin, Danny Marvin Neal, Steven M. Thurber | 2001-04-24 |
| 6134621 | Variable slot configuration for multi-speed bus | Richard Allen Kelley, Danny Marvin Neal, Steven M. Thurber | 2000-10-17 |
| 5701495 | Scalable system interrupt structure for a multi-processing system | Richard Louis Arndt, Edward John Silha, Steven M. Thurber, Amy M. Youngs | 1997-12-23 |
| 5506972 | Computer system having dynamically programmable linear/fairness priority arbitration scheme | Chester A. Heath, James Dalgleish Reid, Frederick E. Strietelmeier | 1996-04-09 |
| 5469463 | Expert system for identifying likely failure points in a digital data processing system | Herman Polich, Larry W. Emlich | 1995-11-21 |
| 5418927 | I/O cache controller containing a buffer memory partitioned into lines accessible by corresponding I/O devices and a directory to track the lines | Albert Chang, George A. Lerom, John C. O'Quin, III, John T. O'Quin, II | 1995-05-23 |
| 5388228 | Computer system having dynamically programmable linear/fairness priority arbitration scheme | Chester A. Heath, James Dalgleish Reid, Frederick E. Strietelmeier | 1995-02-07 |
| 5293622 | Computer system with input/output cache | John C. O'Quin, III, John T. O'Quin, II, Frederick E. Strietelmeier | 1994-03-08 |
| 5287457 | Computer system DMA transfer | Ravi Kumar Arimilli, Sudhir Dhawan, David W. Siegel | 1994-02-15 |
| 5287482 | Input/output cache | Ravi Kumar Arimilli, Sudhir Dhawan, David W. Siegel | 1994-02-15 |
| 5274784 | Data transfer using bus address lines | Ravi Kumar Arimilli, Sudhir Dhawan, David W. Siegel | 1993-12-28 |
| 5251303 | System for DMA block data transfer based on linked control blocks | Richard G. Fogg, Jr., Joseph R. Mathis | 1993-10-05 |
| 5237676 | High speed data transfer system which adjusts data transfer speed in response to indicated transfer speed capability of connected device | Ravi Kumar Arimilli, Sudhir Dhawan, George A. Lerom, David W. Siegel | 1993-08-17 |
| 5161219 | Computer system with input/output cache | John C. O'Quin, III, John T. O'Quin, II, Frederick E. Strietelmeier | 1992-11-03 |
| 5109490 | Data transfer using bus address lines | Ravi Kumar Arimilli, Sudhir Dhawan, David W. Siegel | 1992-04-28 |
| 5090014 | Identifying likely failure points in a digital data processing system | Herman Polich, Larry W. Emlich | 1992-02-18 |