Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10084469 | Control system and method for a configurable analog to digital converter | — | 2018-09-25 |
| 9966900 | Apparatus for oscillator with improved precision and associated methods | Arup Mukherji, John M. Khoury | 2018-05-08 |
| 9689724 | Resonant signal sensing circuit having a low power mode | — | 2017-06-27 |
| 9246494 | Metering circuit including a floating count window to determine a count | — | 2016-01-26 |
| 9166576 | Circuits and methods of automatically adjusting a discriminator threshold | — | 2015-10-20 |
| 9038480 | Integrated circuit and apparatus for detecting oscillations | Michael Keith Odland, Kenneth W. Fernald | 2015-05-26 |
| 8402823 | Low power metering using pulse counting | Michael L. Duffy, Douglas S. Piasecki, Michael Keith Odland | 2013-03-26 |
| 8136409 | Performing metering using pulse counting | — | 2012-03-20 |
| 8023557 | Hardware synchronizer for 802.15.4 radio to minimize processing power consumption | Nicolas Constantinidis, Guillaume Crinon, Alexandre Rouxel, Alan L. Westwick, Gary Franzosa +1 more | 2011-09-20 |
| 7817674 | Output clock adjustment for a digital I/O between physical layer device and media access controller | — | 2010-10-19 |
| 7428599 | Method for detecting link partner state during auto negotiation and switching local state to establish link | Vikas Shahdadpuri | 2008-09-23 |
| 7296085 | Multiple protocol handshaking between systems | Andy Engel, Janet Yun, Allan Liu, Robert T. Grisamore | 2007-11-13 |
| 6604206 | Reduced GMII with internal timing compensation | Mandeep Singh Chadha, Nicholas R. van Bavel | 2003-08-05 |
| 6351804 | Control bit vector storage for a microprocessor | — | 2002-02-26 |
| 6170825 | Dual level board game and method of play | — | 2001-01-09 |
| 6157994 | Microprocessor employing and method of using a control bit vector storage for instruction execution | — | 2000-12-05 |
| 5903910 | Method for transferring data between a pair of caches configured to be accessed from different stages of an instruction processing pipeline | Thang M. Tran, David B. Witt, William M. Johnson | 1999-05-11 |
| 5831462 | Conditional latching mechanism and pipelined microprocessor employing the same | David B. Witt | 1998-11-03 |
| 5822560 | Apparatus for efficient instruction execution via variable issue and variable control vectors per issue | — | 1998-10-13 |
| 5813033 | Superscalar microprocessor including a cache configured to detect dependencies between accesses to the cache and another cache | — | 1998-09-22 |
| 5790821 | Control bit vector storage for storing control vectors corresponding to instruction operations in a microprocessor | — | 1998-08-04 |
| 5787474 | Dependency checking structure for a pair of caches which are accessed from different pipeline stages of an instruction processing pipeline | — | 1998-07-28 |
| 5768610 | Lookahead register value generator and a superscalar microprocessor employing same | — | 1998-06-16 |
| 5684422 | Pipelined microprocessor including a high speed single-clock latch circuit | David B. Witt | 1997-11-04 |