Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8825948 | Memory controller with emulative internal memory buffer | — | 2014-09-02 |
| 7584316 | Packet manager interrupt mapper | — | 2009-09-01 |
| 7475271 | Exponential channelized timer | — | 2009-01-06 |
| 7440469 | Descriptor write back delay mechanism to improve performance | — | 2008-10-21 |
| 7243172 | Fragment storage for data alignment and merger | Laurent Moll | 2007-07-10 |
| 6981074 | Descriptor-based load balancing | Jeremy Dion | 2005-12-27 |
| 6948035 | Data pend mechanism | Joseph B. Rowlands | 2005-09-20 |
| 6941406 | System having interfaces and switch that separates coherent and packet traffic | Barton Sano, Joseph B. Rowlands, James B. Keller, Laurent Moll, Manu Gulati | 2005-09-06 |
| 6941440 | Addressing scheme supporting variable local addressing and variable global addressing | Laurent Moll, James D. Kelly, Manu Gulati, Joseph B. Rowlands | 2005-09-06 |
| 6912602 | System having two or more packet interfaces, a switch, and a shared packet DMA circuit | Barton Sano, Laurent Moll, Manu Gulati | 2005-06-28 |
| 6748479 | System having interfaces and switch that separates coherent and packet traffic | Barton Sano, Joseph B. Rowlands, James B. Keller, Laurent Moll, Manu Gulati | 2004-06-08 |