Issued Patents All Time
Showing 25 most recent of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12235703 | Dynamic voltage margin recovery | Conrad H. Ziesler, Daniel C. Murray, Jong-Suk Lee, Rohit Kumar | 2025-02-25 |
| 11740676 | Dynamic voltage margin recovery | Conrad H. Ziesler, Daniel C. Murray, Jong-Suk Lee, Rohit Kumar | 2023-08-29 |
| 11422606 | Dynamic voltage margin recovery | Conrad H. Ziesler, Daniel C. Murray, Jong-Suk Lee, Rohit Kumar | 2022-08-23 |
| 10990159 | Architected state retention for a frequent operating state switching processor | Bernard J. Semeria, Pradeep Kanapathipillai, Richard F. Russo, Shih-Chieh Wen, Richard H. Larson | 2021-04-27 |
| 10955893 | Dynamic voltage margin recovery | Conrad H. Ziesler, Daniel C. Murray, Jong-Suk Lee, Rohit Kumar | 2021-03-23 |
| 10401938 | Single power plane dynamic voltage margin recovery for multiple clock domains | Jong-Suk Lee, Ramesh Gunna, Shih-Chieh Wen | 2019-09-03 |
| 10101788 | Dynamic voltage margin recovery | Conrad H. Ziesler, Daniel C. Murray, Jong-Suk Lee, Rohit Kumar | 2018-10-16 |
| 9996348 | Zero cycle load | Gerard R. Williams, III, Conrade Blasco-Allue | 2018-06-12 |
| 9606605 | Dynamic voltage margin recovery | Conrad H. Ziesler, Daniel C. Murray, Jong-Suk Lee, Rohit Kumar | 2017-03-28 |
| 9600289 | Load-store dependency predictor PC hashing | Stephan G. Meier, Gerard R. Williams, III, Suparn Vats | 2017-03-21 |
| 9575754 | Zero cycle move | James B. Keller, Conrado Blasco-Allue, Gerard R. Williams, III, Suparn Vats | 2017-02-21 |
| 9535695 | Completing load and store instructions in a weakly-ordered memory model | Rajat Goel, Pradeep Kanapathipillai, Hari Kannan | 2017-01-03 |
| 9430243 | Optimizing register initialization operations | James B. Keller, Conrado Blasco-Allue, Gerard R. Williams, III | 2016-08-30 |
| 9354879 | System and method for register renaming with register assignment based on an imbalance in free list banks | Suparn Vats, Abhijit Radhakrishnan | 2016-05-31 |
| 9336003 | Multi-level dispatch for a superscalar processor | Gerard R. Williams, III, Shyam Balasubramanian, Conrado Blasco-Allue | 2016-05-10 |
| 9317285 | Instruction set architecture mode dependent sub-size access of register with associated status indication | Sandeep Gupta, Conrado Blasco-Allue, Gerard R. Williams, III, James B. Keller | 2016-04-19 |
| 9223577 | Processing multi-destination instruction in pipeline by splitting for single destination operations stage and merging for opcode execution operations stage | Gerard R. Williams, III, James B. Keller, Fang Liu, Shyam Sundar | 2015-12-29 |
| 9128725 | Load-store dependency predictor content management | Stephan G. Meier, Gerard R. Williams, III, Suparn Vats | 2015-09-08 |
| 9009451 | Instruction type issue throttling upon reaching threshold by adjusting counter increment amount for issued cycle and decrement amount for not issued cycle | Daniel C. Murray, Andrew J. Beaumont-Smith, Peter J. Bannon, Toshi Takayanagi, Jung Wook Cho | 2015-04-14 |
| 8769332 | Regional clock gating and dithering | Conrad H. Ziesler, Jason M. Kassoff | 2014-07-01 |
| 8621412 | Micro-regions for auto place and route optimization | Suparn Vats, Karthik Rajagopal | 2013-12-31 |
| 8583967 | Program counter (PC) trace | Kevin R. Walker | 2013-11-12 |
| 8381041 | Program counter (PC) trace | Kevin R. Walker | 2013-02-19 |
| 8364936 | Processor employing split scheduler in which near, low latency operation dependencies are tracked separate from other operation dependencies | Andrew J. Beaumont-Smith, Honkai Tam, Daniel C. Murray, Peter J. Bannon, Pradeep Kanapathipillai | 2013-01-29 |
| 8285947 | Store hit load predictor | Andrew J. Beaumont-Smith | 2012-10-09 |