Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9753733 | Methods, apparatus, and processors for packing multiple iterations of loop in a loop buffer | Ian D. Kountanis | 2017-09-05 |
| 9672037 | Arithmetic branch fusion | Sandeep Gupta | 2017-06-06 |
| 9626185 | IT instruction pre-decode | Shyam Sundar, Ian D. Kountanis, Gerard R. Williams, III, Wei-Han Lien, Ramesh Gunna | 2017-04-18 |
| 9575754 | Zero cycle move | James B. Keller, John H. Mylius, Gerard R. Williams, III, Suparn Vats | 2017-02-21 |
| 9557999 | Loop buffer learning | Ian D. Kountanis | 2017-01-31 |
| 9430243 | Optimizing register initialization operations | James B. Keller, John H. Mylius, Gerard R. Williams, III | 2016-08-30 |
| 9405544 | Next fetch predictor return address stack | Douglas C. Holman, Ramesh Gunna | 2016-08-02 |
| 9367471 | Fetch width predictor | Ramesh Gunna | 2016-06-14 |
| 9336003 | Multi-level dispatch for a superscalar processor | John H. Mylius, Gerard R. Williams, III, Shyam Balasubramanian | 2016-05-10 |
| 9317285 | Instruction set architecture mode dependent sub-size access of register with associated status indication | Sandeep Gupta, John H. Mylius, Gerard R. Williams, III, James B. Keller | 2016-04-19 |
| 9311098 | Mechanism for reducing cache power consumption using cache way prediction | Ronald P. Hall | 2016-04-12 |
| 9311100 | Usefulness indication for indirect branch prediction training | Sandeep Gupta, Shyam Sundar, Wei-Han Lien, Gerard R. Williams, III | 2016-04-12 |
| 9311084 | RDA checkpoint optimization | Shyam Sundar | 2016-04-12 |