Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10324509 | Automatic generation of power management sequence in a SoC or NoC | Anup Gangwar, Vishnu Mohan Pusuluri, Sailesh Kumar | 2019-06-18 |
| 10074053 | Clock gating for system-on-chip elements | Sailesh Kumar, Sandip Das | 2018-09-11 |
| 10042404 | Automatic generation of power management sequence in a SoC or NoC | Anup Gangwar, Vishnu Mohan Pusuluri, Sailesh Kumar | 2018-08-07 |
| 9571341 | Clock gating for system-on-chip elements | Sailesh Kumar, Sandip Das | 2017-02-14 |
| 9477280 | Specification for automatic power management of network-on-chip and system-on-chip | Anup Gangwar, Vishnu Mohan Pusuluri, Sailesh Kumar | 2016-10-25 |
| 7136308 | Efficient method of data transfer between register files and memories | Shree Kant, Kenway Tam, Yuan Lin, Zhen Liu, Kathirgamar Aingaran | 2006-11-14 |
| 6895561 | Power modeling methodology for a pipelined processor | Miriam G. Blatt, David Greenhill, Vidyasagar Ganesan | 2005-05-17 |
| 6862676 | Superscalar processor having content addressable memory structures for determining dependencies | Micah C. Knapp, Marc Lamere, Julie M. Staraitis | 2005-03-01 |
| 6662293 | Instruction dependency scoreboard with a hierarchical structure | Richard H. Larson, Sanjay Patel, Daniel Leibholz | 2003-12-09 |
| 6078987 | Translation look aside buffer having separate RAM arrays which are accessable with separate enable signals | — | 2000-06-20 |
| 5936873 | Single ended match sense amplifier | — | 1999-08-10 |