Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8482316 | Adaptive timing control circuitry to address leakage | Zhen Liu, Heechoul Park | 2013-07-09 |
| 7484061 | Method for performing swap operation and apparatus for implementing the same | Zhen Liu, Kenway Tam | 2009-01-27 |
| 7337305 | Method and pipeline architecture for processing multiple swap requests to reduce latency | Kenway Tam | 2008-02-26 |
| 7203100 | Efficient implementation of a read scheme for multi-threaded register file | Kathirgamar Aingaran, Yuan Lin, Kenway Tam | 2007-04-10 |
| 7136308 | Efficient method of data transfer between register files and memories | Kenway Tam, Poonacha Kongetira, Yuan Lin, Zhen Liu, Kathirgamar Aingaran | 2006-11-14 |
| 6940771 | Methods and circuits for balancing bitline precharge | Aparna Ramachandran, Ranjan Vaish | 2005-09-06 |
| 6900668 | High speed single ended sense amplifier with built-in multiplexer | Kenway Tam | 2005-05-31 |
| 6707721 | Low power memory design with asymmetric bit line driver | Gajendra Prasad Singh, Aparna Ramachandran, Miao Rao | 2004-03-16 |
| 6646951 | High performance address decode technique for arrays | Aparna Ramachandran | 2003-11-11 |
| 6442099 | Low power read scheme for memory array structures | Gajendra Prasad Singh | 2002-08-27 |
| 6320813 | Decoding of a register file | — | 2001-11-20 |
| 6316301 | Method for sizing PMOS pull-up devices | — | 2001-11-13 |
| 6038193 | Single ended read scheme with segmented bitline of multi-port register file | Yong Wang | 2000-03-14 |
| 6014338 | Single ended read scheme with global bitline of multi-port register file | Yong Wang | 2000-01-11 |