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Nitin Agarwal, Honnahuggi Harinath Venkata Naga Ambica Prasad, Narayana Sri Harsha Gade, Ravishankar Sreedharan |
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| 10817627 |
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Nitin Agarwal, Honnahuggi Harinath Venkata Naga Ambica Prasad, Ravishankar Sreedharan |
2020-10-27 |
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Virtual channel assignment for topology constrained network-on-chip design |
Nitin Agarwal, Zheng Xu |
2020-09-29 |
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Nitin Agarwal |
2020-04-28 |
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Integrated circuit design |
Nitin Agarwal, Honnahuggi Harinath Venkata Naga Ambica Prasad |
2020-04-21 |
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Automatic generation of power management sequence in a SoC or NoC |
Vishnu Mohan Pusuluri, Poonacha Kongetira, Sailesh Kumar |
2019-06-18 |
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Integrated circuit design |
Nitin Agarwal |
2019-06-11 |
| 10042404 |
Automatic generation of power management sequence in a SoC or NoC |
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2018-08-07 |
| 9829962 |
Hardware and software enabled implementation of power profile management instructions in system on chip |
Rimu Kaushal, Vishnu Mohan Pusuluri, Sailesh Kumar |
2017-11-28 |
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Vishnu Mohan Pusuluri, Santhosh Patchamatla, Rimu Kaushal, Sailesh Kumar |
2017-10-10 |
| 9568970 |
Hardware and software enabled implementation of power profile management instructions in system on chip |
Rimu Kaushal, Vishnu Mohan Pusuluri, Sailesh Kumar |
2017-02-14 |
| 9477280 |
Specification for automatic power management of network-on-chip and system-on-chip |
Vishnu Mohan Pusuluri, Poonacha Kongetira, Sailesh Kumar |
2016-10-25 |