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Home › Method and apparatus for optimizing the performance of LDxL and STxC interlock instructions in the context of a write invalidate protocol

Method and apparatus for optimizing the performance of LDxL and STxC interlock instructions in the context of a write invalidate protocol

US Patent 6141734 · Granted Oct 31, 2000

Estimated economic value: $170,498,000 ⓘ

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