Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12248413 | Universal memory interface utilizing die-to-die (D2D) interfaces between chiplets | Ramin Farjadrad, Syrus Ziai | 2025-03-11 |
| 12204468 | Universal memory interface with dynamic bidirectional data transfers | Syrus Ziai | 2025-01-21 |
| 12182040 | Multi-chip module (MCM) with scalable high bandwidth memory | Ramin Farjadrad, Syrus Ziai, Kevin S. Donnelly | 2024-12-31 |
| 11671017 | Current balancing for voltage regulator units in field programmable arrays | Gang Ren, Peng Zou, Syrus Ziai | 2023-06-06 |
| 11658577 | Power management integrated circuit with a field programmable array of voltage regulators | Peng Zou, Gang Ren, Syrus Ziai | 2023-05-23 |
| 7532003 | Method and apparatus for setting VDD on a per chip basis | David Greenhill, Thomas Caron, Shanker Bhagvat | 2009-05-12 |
| 7454631 | Method and apparatus for controlling power consumption in multiprocessor chip | James Laudon | 2008-11-18 |
| 7028150 | Arrangement of data within cache lines so that tags are first data received | Robert C. Douglas, Henry Yu | 2006-04-11 |
| 6928520 | Memory controller that provides memory line caching and memory transaction coherency by using at least one memory controller agent | Robert C. Douglas | 2005-08-09 |
| 6865634 | Method and apparatus for deadlock prevention in a distributed shared memory system | — | 2005-03-08 |
| 6785778 | Share masks and alias for directory coherency | — | 2004-08-31 |
| 6671792 | Share masks and alias for directory coherency | — | 2003-12-30 |
| 6651124 | Method and apparatus for preventing deadlock in a distributed shared memory system | — | 2003-11-18 |
| 6611906 | Self-organizing hardware processing entities that cooperate to execute requests | Robert C. Douglas | 2003-08-26 |
| 6598140 | Memory controller having separate agents that process memory transactions in parallel | Robert C. Douglas | 2003-07-22 |
| 6564306 | Apparatus and method for performing speculative cache directory tag updates | Michael K. Dugan, Gary Gostin, Mark A. Heap, Terry Huang, Henry Yu | 2003-05-13 |
| 6463506 | Arrangement of data within cache lines so that tags are first data received | Robert C. Douglas, Henry Yu | 2002-10-08 |
| 6073223 | Memory controller and method for intermittently activating and idling a clock signal for a synchronous memory | Leith L. Johnson | 2000-06-06 |
| 5347634 | System and method for directly executing user DMA instruction from user controlled process by employing processor privileged work buffer pointers | Russ W. Herrell, Dong-Ying Kuo, Christopher G. Wilcox | 1994-09-13 |