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Method for training multichannel data receiver timing |
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Narrow-parallel scan-based device testing |
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Multi-dimensional integrated circuit structures and methods of forming the same |
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| 9054101 |
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| 8686570 |
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Method for storing prioritized memory or I/O transactions in queues having one priority level less without changing the priority when space available in the corresponding queues exceed |
William K. Zuravleff, Timothy B. Robinson, Scott Furman |
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Non-blocking load buffer and a multiple-priority memory system for real-time multiprocessing |
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System for placing entries of an outstanding processor request into a free pool after the request is accepted by a corresponding peripheral device |
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Processor system with dual clock |
James S. Blomgren, Tuan Luong, Gary Baum |
1995-01-10 |
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Processor system with dual clock |
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Computer system architecture implementing split instruction and operand cache line-pair-state management |
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1988-05-17 |
