Issued Patents All Time
Showing 1–25 of 107 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12425224 | Device with self-authentication | Haohua Zhou | 2025-09-23 |
| 12406123 | System and method for ESL modeling of machine learning | Kai-Yuan Ting, Tze-Chiang Huang, Yun-Han Lee | 2025-09-02 |
| 12399211 | Method of testing an integrated circuit and testing system | Ankita Patidar, Yun-Han Lee | 2025-08-26 |
| 12385973 | Scan architecture for interconnect testing in 3D integrated circuits | Yun-Han Lee, Saman M. I. Adham, Marat Gershoig | 2025-08-12 |
| 12368684 | Network-on-chip system and a method of generating the same | Ravi Venugopalan, Yun-Han Lee | 2025-07-22 |
| 12346147 | Circuit and methodology for power profile | Ankita Patidar, Yun-Han Lee | 2025-07-01 |
| 12314644 | Integrated circuit design method, system and computer program product | Ankita Patidar, Yun-Han Lee | 2025-05-27 |
| 12306248 | Scan chains with multi-bit cells and methods for testing the same | Mohammed Moiz Khan | 2025-05-20 |
| 12229483 | Method and system for reducing migration errors | Ankita Patidar, Yun-Han Lee | 2025-02-18 |
| 12204825 | Function safety and fault management modeling at electrical system level (ESL) | Kai-Yuan Ting, Hsin-Cheng Chen, Mei Hsu Wong, Yun-Han Lee | 2025-01-21 |
| 12066490 | Wrapper cell design and built-in self-test architecture for 3DIC test and diagnosis | Anshuman Chandra | 2024-08-20 |
| 12014130 | System and method for ESL modeling of machine learning | Kai-Yuan Ting, Tze-Chiang Huang, Yun-Han Lee | 2024-06-18 |
| 11899064 | Scan architecture for interconnect testing in 3D integrated circuits | Yun-Han Lee, Saman M. I. Adham, Marat Gershoig | 2024-02-13 |
| 11879933 | Method of testing an integrated circuit and testing system | Ankita Patidar, Yun-Han Lee | 2024-01-23 |
| 11837308 | Systems and methods to detect cell-internal defects | Ankita Patidar | 2023-12-05 |
| 11831781 | Device with self-authentication | Haohua Zhou | 2023-11-28 |
| 11727177 | Integrated circuit design method, system and computer program product | Ankita Patidar, Yun-Han Lee | 2023-08-15 |
| 11699010 | Method and system for reducing migration errors | Ankita Patidar, Yun-Han Lee | 2023-07-11 |
| 11663387 | Fault diagnostics | Ankita Patidar | 2023-05-30 |
| 11585831 | Test probing structure | Mill-Jer Wang, Ching-Fang Chen, Chung-Sheng Yuan, Chao-Yang Yeh, Chin-Chou Liu +2 more | 2023-02-21 |
| 11549984 | Scan architecture for interconnect testing in 3D integrated circuits | Yun-Han Lee, Saman M. I. Adham, Marat Gershoig | 2023-01-10 |
| 11496417 | Network-on-chip system and a method of generating the same | Ravi Venugopalan, Yun-Han Lee | 2022-11-08 |
| 11411571 | Phase-locked loop monitor circuit | Ji-Jan Chen, Stanley John, Yun-Han Lee, Yen-Hao Huang | 2022-08-09 |
| 11386253 | Power-aware scan partitioning | Ankita Patidar, Yun-Han Lee | 2022-07-12 |
| 11379643 | Integrated circuit design method, system and computer program product | Ankita Patidar, Yun-Han Lee | 2022-07-05 |