Issued Patents All Time
Showing 1–25 of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12272691 | Semiconductor and circuit structures, and related methods | Chang-Fen Hu, Shao-Yu Li, Kuo-Ji Chen, Chih-Peng Lin, Chuei-Tang Wang | 2025-04-08 |
| 12253558 | Circuit test structure and method of using | Hsiang-Tai Lu, Chih-Hsien Lin | 2025-03-18 |
| 12154851 | Method of forming a semiconductor device with inter-layer vias | Yi-Lin Chuang, Jia-Jye Shen | 2024-11-26 |
| 11828790 | Circuit test structure and method of using | Hsiang-Tai Lu, Chih-Hsien Lin | 2023-11-28 |
| 11699683 | Semiconductor device in 3D stack with communication interface and managing method thereof | Igor Elkanovich, Amnon Parnass, Pei-Ling Yu, Li-Ken Yeh, Yung-Sheng Fang +3 more | 2023-07-11 |
| 11687472 | Interface for semiconductor device and interfacing method thereof | Igor Elkanovich, Amnon Parnass, Pei-Ling Yu, Li-Ken Yeh, Yung-Sheng Fang +3 more | 2023-06-27 |
| 11675731 | Data protection system and method thereof for 3D semiconductor device | Igor Elkanovich, Amnon Parnass, Pei-Ling Yu, Li-Ken Yeh, Yung-Sheng Fang +3 more | 2023-06-13 |
| 11646313 | Semiconductor and circuit structures, and related methods | Chang-Fen Hu, Shao-Yu Li, Kuo-Ji Chen, Chih-Peng Lin, Chuei-Tang Wang | 2023-05-09 |
| 11585831 | Test probing structure | Mill-Jer Wang, Sandeep Kumar Goel, Chung-Sheng Yuan, Chao-Yang Yeh, Chin-Chou Liu +2 more | 2023-02-21 |
| 11200364 | Method and associated system for circuit design | Chia-Cheng Chen, Huang-Yu Chen, Jen Ping Hsu | 2021-12-14 |
| 11144485 | Interface for semiconductor device with symmetric bond pattern and method for arranging interface thereof | Igor Elkanovich, Amnon Parnass, Pei-Ling Yu, Li-Ken Yeh, Yung-Sheng Fang +3 more | 2021-10-12 |
| 11114376 | System for layout design of structure with inter layer vias | Yi-Lin Chuang, Jia-Jye Shen | 2021-09-07 |
| 11031923 | Interface device and interface method for 3D semiconductor device | Igor Elkanovich, Amnon Parnass, Pei-Ling Yu, Li-Ken Yeh, Yung-Sheng Fang +3 more | 2021-06-08 |
| 11017149 | Machine-learning design enablement platform | Yi-Lin Chuang, Wei-Li Chen, Wei-Pin Changchien, Yung-Chin Hou, Yun-Han Lee | 2021-05-25 |
| 11002788 | Circuit test structure | Hsiang-Tai Lu, Chih-Hsien Lin | 2021-05-11 |
| 10782318 | Test probing structure | Mill-Jer Wang, Sandeep Kumar Goel, Chung-Sheng Yuan, Chao-Yang Yeh, Chin-Chou Liu +2 more | 2020-09-22 |
| 10678973 | Machine-learning design enablement platform | Yi-Lin Chuang, Wei-Li Chen, Wei-Pin Changchien, Yung-Chin Hou, Yun-Han Lee | 2020-06-09 |
| 10566278 | Method for layout design and structure with inter-layer vias | Yi-Lin Chuang, Jia-Jye Shen | 2020-02-18 |
| 10288676 | Circuit test structure | Hsiang-Tai Lu, Chih-Hsien Lin | 2019-05-14 |
| 9952279 | Apparatus for three dimensional integrated circuit testing | Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Hao Chen, Chung-Han Huang +3 more | 2018-04-24 |
| 9817029 | Test probing structure | Mill-Jer Wang, Sandeep Kumar Goel, Chung-Sheng Yuan, Chao-Yang Yeh, Chin-Chou Liu +2 more | 2017-11-14 |
| 9689914 | Method of testing a three-dimensional integrated circuit | Hsiang-Tai Lu, Chih-Hsien Lin | 2017-06-27 |
| 9679840 | Method for layout design and structure with inter-layer vias | Yi-Lin Chuang, Jia-Jye Shen | 2017-06-13 |
| 9613174 | Common template for electronic article | William Wu Shen, Yun-Han Lee, Chin-Chou Liu, Hsien-Hsin Sean Lee, Chung-Sheng Yuan +2 more | 2017-04-04 |
| 9040986 | Three dimensional integrated circuit having a resistance measurement structure and method of use | Hsiang-Tai Lu, Chih-Hsien Lin | 2015-05-26 |