Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12154851 | Method of forming a semiconductor device with inter-layer vias | Yi-Lin Chuang, Ching-Fang Chen | 2024-11-26 |
| 11114376 | System for layout design of structure with inter layer vias | Yi-Lin Chuang, Ching-Fang Chen | 2021-09-07 |
| 10566278 | Method for layout design and structure with inter-layer vias | Yi-Lin Chuang, Ching-Fang Chen | 2020-02-18 |
| 9679840 | Method for layout design and structure with inter-layer vias | Yi-Lin Chuang, Ching-Fang Chen | 2017-06-13 |
| 6519749 | Integrated circuit partitioning placement and routing system | Ping Chao, Wei-Jin Dai, Mitsuru Igusa, Wei-Lun Kao | 2003-02-11 |