Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11818263 | Computing key rotation period for block cipher-based encryption schemes system and method | Atul Luykx | 2023-11-14 |
| 11804960 | Distributed symmetric encryption | Pratyay Mukherjee, Shashank Agrawal, Peter Rindal, Atul Luykx | 2023-10-31 |
| 11438152 | Distributed symmetric encryption | Pratyay Mukherjee, Shashank Agrawal, Peter Rindal, Atul Luykx | 2022-09-06 |
| 8095898 | Method and system for implementing electronic design entry | Ping-Chih Wu, Lung-Chun Liu, Thad McCracken | 2012-01-10 |
| 6782520 | IC layout system having separate trial and detailed routing phases | Mitsuru Igusa, Shiu-Ping Chao, Dennis Huang | 2004-08-24 |
| 6782519 | Clock tree synthesis for mixed domain clocks | Jui-Ming Chang, Chin-Chi Teng | 2004-08-24 |
| 6751786 | Clock tree synthesis for a hierarchically partitioned IC layout | Chin-Chi Teng | 2004-06-15 |
| 6651235 | Scalable, partitioning integrated circuit layout system | Kit Lam Cheong, Hsi-Chuan Chen, Wei-Lun Kao | 2003-11-18 |
| 6578183 | Method for generating a partitioned IC layout | Kit Lam Cheong, Hsi-Chuan Chen, Patrick John Eichenseer | 2003-06-10 |
| 6519749 | Integrated circuit partitioning placement and routing system | Ping Chao, Mitsuru Igusa, Wei-Lun Kao, Jia-Jye Shen | 2003-02-11 |
| 6249902 | Design hierarchy-based placement | Mitsuru Igusa, Hsi-Chuan Chen, Shiu-Ping Chao, Daw Yang Shyong | 2001-06-19 |
| 5886904 | Latch optimization in hardware logic emulation systems | Junjing Yan | 1999-03-23 |
| 5452239 | Method of removing gated clocks from the clock nets of a netlist for timing sensitive implementation of the netlist in a hardware emulation system | Louis Galbiati, III, Joseph Varghese, Dam Van Bui, Stephen P. Sample | 1995-09-19 |