Issued Patents All Time
Showing 25 most recent of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9645951 | Accelerator system for remote data storage | Michael H. Wang, Steven Mark Casselman, Babu Rao Kandimalla, Lawrence A. Laurich | 2017-05-09 |
| 9411524 | Accelerator system for use with secure data storage | Mark S. O'Hare, Rick L. Orsini, Lawrence A. Laurich, Michael H. Wang, Babu Rao Kandimalla +2 more | 2016-08-09 |
| 8824492 | Accelerator system for remote data storage | Michael H. Wang, Steven Mark Casselman, Babu Rao Kandimalla, Lawrence A. Laurich | 2014-09-02 |
| 8601498 | Accelerator system for use with secure data storage | Lawrence A. Laurich, Michael H. Wang, Babu Rao Kandimalla, Rick L. Orsini, Mark S. O'Hare +2 more | 2013-12-03 |
| 7856546 | Configurable processor module accelerator using a programmable logic device | Steven Mark Casselman | 2010-12-21 |
| 7739097 | Emulation system with time-multiplexed interconnect | Mikhail Bershteyn, Michael Butts, Jerry R. Bauer | 2010-06-15 |
| 6882176 | High-performance programmable logic architecture | Kevin A. Norman, Rakesh Patel, Michael Butts | 2005-04-19 |
| 6842729 | Apparatus for emulation of electronic systems | Michael R. D'Amour, Thomas S. Payne | 2005-01-11 |
| 6732068 | Memory circuit for use in hardware emulation system | Mikhail Bershteyn, Michael Butts, Jerry R. Bauer | 2004-05-04 |
| 6694464 | Method and apparatus for dynamically testing electrical interconnect | Barton L. Quayle | 2004-02-17 |
| 6625793 | Optimized emulation and prototyping architecture | Michael Butts | 2003-09-23 |
| 6570404 | High-performance programmable logic architecture | Kevin A. Norman, Rakesh Patel, Michael Butts | 2003-05-27 |
| 6567967 | Method for designing large standard-cell base integrated circuits | Yaacov Greidinger, David S. Reed, Ara Markosian, Jonathan Frankle, Hasmik Lazaryan | 2003-05-20 |
| 6377911 | Apparatus for emulation of electronic hardware system | Michael R. D'Amour, Thomas S. Payne | 2002-04-23 |
| 6377912 | Emulation system with time-multiplexed interconnect | Mikhail Bershteyn, Michael Butts, Jerry R. Bauer | 2002-04-23 |
| 6353552 | PLD with on-chip memory having a shadow register | Michael Butts, Kevin A. Norman, Rakesh Patel, Chao-Chiang Chen | 2002-03-05 |
| 6317367 | FPGA with on-chip multiport memory | Michael Butts, Kevin A. Norman, Rakesh Patel, Chao-Chiang Chen | 2001-11-13 |
| 6289494 | Optimized emulation and prototyping architecture | Michael Butts | 2001-09-11 |
| 6285211 | I/O buffer circuit with pin multiplexing | Michael Butts, Kevin A. Norman, Rakesh Patel | 2001-09-04 |
| 6259588 | Input/output buffer with overcurrent protection circuit | Michael Butts, Kevin A. Norman, Rakesh Patel | 2001-07-10 |
| 6219284 | Programmable logic device with multi-port memory | Michael Butts, Kevin A. Norman, Rakesh Patel, Chao-Chiang Chen | 2001-04-17 |
| 6184707 | Look-up table based logic element with complete permutability of the inputs to the secondary signals | Kevin A. Norman, Rakesh Patel, Michael Butts | 2001-02-06 |
| 6151258 | Programmable logic device with multi-port memory | Michael Butts, Kevin A. Norman, Rakesh Patel, Chao-Chiang Chen | 2000-11-21 |
| 6058492 | Method and apparatus for design verification using emulation and simulation | Mikhail Bershteyn | 2000-05-02 |
| 6034857 | Input/output buffer with overcurrent protection circuit | Michael Butts, Kevin A. Norman, Rakesh Patel | 2000-03-07 |