Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7687303 | Method for determining via/contact pattern density effect in via/contact etch rate | Valeriy Sukharev | 2010-03-30 |
| 6567967 | Method for designing large standard-cell base integrated circuits | Yaacov Greidinger, David S. Reed, Stephen P. Sample, Jonathan Frankle, Hasmik Lazaryan | 2003-05-20 |
| 6449761 | Method and apparatus for providing multiple electronic design solutions | Yaacov (Jacob) Greidinger, Jon Frankle | 2002-09-10 |
| 6446239 | Method and apparatus for optimizing electronic design | Yaacov (Jacob) Greidinger, Siu-Tong Hui, Sedrak Sargisian | 2002-09-03 |
| 5856927 | Method for automatically routing circuits of very large scale integration (VLSI) | Jacob Greidinger, Mark R. Hartoog, Christine Fawcett, Eugenia Gelfund, Prasad Sakhamuri | 1999-01-05 |