PE

Patrick John Eichenseer

CS Cadence Design Systems: 5 patents #303 of 2,263Top 15%
SP Silicon Perspective: 1 patents #4 of 11Top 40%
Overall (All Time): #866,859 of 4,157,543Top 25%
6
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
8051397 Method and system for conducting design explorations of an integrated circuit Thaddeus Clay McCracken, Jong-Chang Lee, Ping-Chih Wu, Cecile Nghiem, Kit Lam Cheong 2011-11-01
7793254 Method and system for designing a timing closure of an integrated circuit Ricky Lewelling, Ziad Sadi 2010-09-07
7603643 Method and system for conducting design explorations of an integrated circuit Thaddeus Clay McCracken, Jong-Chang Lee, Ping-Chih Wu, Cecile Nghiem, Kit Lam Cheong 2009-10-13
7257798 Method and system for designing a timing closure of an integrated circuit Ricky Lewelling, Ziad Sadi 2007-08-14
7155694 Trial placement system with cloning Hsi-Chuan Chen, Dennis Huang 2006-12-26
6578183 Method for generating a partitioned IC layout Kit Lam Cheong, Wei-Jin Dai, Hsi-Chuan Chen 2003-06-10