Issued Patents All Time
Showing 1–25 of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12419230 | Porous ceramic member with nano silver coating for filtering a plant growth medium and method of application | — | 2025-09-23 |
| 9529034 | Real-time insulation detector for feeding high-frequency low-voltage signal of power system | Tien-Jen Chen | 2016-12-27 |
| 9518304 | Nicotine resistant microorganisms | Peter Majeranowski, Igor Kostenyuk, Iulian Bobe | 2016-12-13 |
| 7917881 | Timing of a circuit design | Chih-Liang Cheng, Chung-Do Yang, Jeong-Tyng Li | 2011-03-29 |
| 7739630 | Optimizing a circuit design | Chih-Liang Cheng, Chung-Do Yang, Jeong-Tyng Li | 2010-06-15 |
| 7155694 | Trial placement system with cloning | Patrick John Eichenseer, Dennis Huang | 2006-12-26 |
| 6774488 | Low leakage and low resistance for memory and the manufacturing method for the plugs | Wen-Kuei Huang | 2004-08-10 |
| 6651235 | Scalable, partitioning integrated circuit layout system | Wei-Jin Dai, Kit Lam Cheong, Wei-Lun Kao | 2003-11-18 |
| 6578183 | Method for generating a partitioned IC layout | Kit Lam Cheong, Wei-Jin Dai, Patrick John Eichenseer | 2003-06-10 |
| 6423594 | Method of fabricating deep trench capacitor | Hong-Hsiang Tsai | 2002-07-23 |
| 6352896 | Method of manufacturing DRAM capacitor | Haochieh Liu, Jung-Ho Chang, Hong-Hsiang Tsai, Li-Ming Wang, Sen-Huan Huang +2 more | 2002-03-05 |
| 6291355 | Method of fabricating a self-aligned contact opening | Haochieh Liu, Bor-Ru Sheu, Sen-Huan Huang | 2001-09-18 |
| 6249902 | Design hierarchy-based placement | Mitsuru Igusa, Shiu-Ping Chao, Wei-Jin Dai, Daw Yang Shyong | 2001-06-19 |
| 6194265 | Process for integrating hemispherical grain silicon and a nitride-oxide capacitor dielectric layer for a dynamic random access memory capacitor structure | Jung-Ho Chang, Dahcheng Lin | 2001-02-27 |
| 6187627 | Lading plug contact pattern for DRAM application | Sen-Huan Huang | 2001-02-13 |
| 6165830 | Method to decrease capacitance depletion, for a DRAM capacitor, via selective deposition of a doped polysilicon layer on a selectively formed hemispherical grain silicon layer | Dahcheng Lin, Jung-Ho Chang | 2000-12-26 |
| 6130146 | In-situ nitride and oxynitride deposition process in the same chamber | Jung-Ho Chang, Dahcheng Lin | 2000-10-10 |
| 6127221 | In situ, one step, formation of selective hemispherical grain silicon layer, and a nitride-oxide dielectric capacitor layer, for a DRAM application | Dahcheng Lin, Jung-Ho Chang | 2000-10-03 |
| 6074931 | Process for recess-free planarization of shallow trench isolation | Jung-Ho Chang, Dahcheng Lin | 2000-06-13 |
| 6046083 | Growth enhancement of hemispherical grain silicon on a doped polysilicon storage node capacitor structure, for dynamic random access memory applications | Dahcheng Lin, Jung-Ho Chang, Kuo-Shu Tseng | 2000-04-04 |
| 6037238 | Process to reduce defect formation occurring during shallow trench isolation formation | Jung-Ho Chang, Dahcheng Lin | 2000-03-14 |
| 6037219 | One step in situ doped amorphous silicon layers used for selective hemispherical grain silicon formation for crown shaped capacitor applications | Dahcheng Lin, Jung-Ho Chang, Kuo-Shu Tseng | 2000-03-14 |
| 5930625 | Method for fabricating a stacked, or crown shaped, capacitor structure | Dahcheng Lin, Jung-Ho Chang | 1999-07-27 |
| 5913119 | Method of selective growth of a hemispherical grain silicon layer on the outer sides of a crown shaped DRAM capacitor structure | Dahcheng Lin, Jung-Ho Chang | 1999-06-15 |
| 5897352 | Method of manufacturing hemispherical grained polysilicon with improved adhesion and reduced capacitance depletion | Dahcheng Lin, Jung-Ho Chang | 1999-04-27 |