Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12254245 | Method of processing digitalized drawing data and computer program | Dong Yong Oh, John G Roby, Sang Do Kim | 2025-03-18 |
| 11251273 | Non-volatile memory device and method for manufacturing the same | Jian-Ting Chen, Yao-Ting Tsai, Hsiu-Han Liao | 2022-02-15 |
| 10971508 | Integrated circuit and method of manufacturing the same | Yao-Ting Tsai, Che-Fu Chuang, Hsiu-Han Liao | 2021-04-06 |
| 6352896 | Method of manufacturing DRAM capacitor | Haochieh Liu, Hsi-Chuan Chen, Hong-Hsiang Tsai, Li-Ming Wang, Sen-Huan Huang +2 more | 2002-03-05 |
| 6194265 | Process for integrating hemispherical grain silicon and a nitride-oxide capacitor dielectric layer for a dynamic random access memory capacitor structure | Hsi-Chuan Chen, Dahcheng Lin | 2001-02-27 |
| 6165830 | Method to decrease capacitance depletion, for a DRAM capacitor, via selective deposition of a doped polysilicon layer on a selectively formed hemispherical grain silicon layer | Dahcheng Lin, Hsi-Chuan Chen | 2000-12-26 |
| 6130146 | In-situ nitride and oxynitride deposition process in the same chamber | Hsi-Chuan Chen, Dahcheng Lin | 2000-10-10 |
| 6127221 | In situ, one step, formation of selective hemispherical grain silicon layer, and a nitride-oxide dielectric capacitor layer, for a DRAM application | Dahcheng Lin, Hsi-Chuan Chen | 2000-10-03 |
| 6074931 | Process for recess-free planarization of shallow trench isolation | Hsi-Chuan Chen, Dahcheng Lin | 2000-06-13 |
| 6046083 | Growth enhancement of hemispherical grain silicon on a doped polysilicon storage node capacitor structure, for dynamic random access memory applications | Dahcheng Lin, Hsi-Chuan Chen, Kuo-Shu Tseng | 2000-04-04 |
| 6037238 | Process to reduce defect formation occurring during shallow trench isolation formation | Hsi-Chuan Chen, Dahcheng Lin | 2000-03-14 |
| 6037219 | One step in situ doped amorphous silicon layers used for selective hemispherical grain silicon formation for crown shaped capacitor applications | Dahcheng Lin, Hsi-Chuan Chen, Kuo-Shu Tseng | 2000-03-14 |
| 5930625 | Method for fabricating a stacked, or crown shaped, capacitor structure | Dahcheng Lin, Hsi-Chuan Chen | 1999-07-27 |
| 5913119 | Method of selective growth of a hemispherical grain silicon layer on the outer sides of a crown shaped DRAM capacitor structure | Dahcheng Lin, Hsi-Chuan Chen | 1999-06-15 |
| 5897352 | Method of manufacturing hemispherical grained polysilicon with improved adhesion and reduced capacitance depletion | Dahcheng Lin, Hsi-Chuan Chen | 1999-04-27 |
| 5877052 | Resolution of hemispherical grained silicon peeling and row-disturb problems for dynamic random access memory, stacked capacitor structures | Dahcheng Lin, Hsi-Chuan Chen, Kuo-Shu Tseng | 1999-03-02 |