Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6822283 | Low temperature MIM capacitor for mixed-signal/RF applications | Min-hwa Chi | 2004-11-23 |
| 6372572 | Method of planarizing peripheral circuit region of a DRAM | Chih-Hsing Yu | 2002-04-16 |
| 6294437 | Method of manufacturing crown-shaped DRAM capacitor | — | 2001-09-25 |
| 6291294 | Method for making a stack bottom storage node having reduced crystallization of amorphous polysilicon | — | 2001-09-18 |
| 6240015 | Method for reading 2-bit ETOX cells using gate induced drain leakage current | Min-hwa Chi | 2001-05-29 |
| 6225214 | Method for forming contact plug | — | 2001-05-01 |
| 6197652 | Fabrication method of a twin-tub capacitor | Chih-Hsing Yu | 2001-03-06 |
| 6194265 | Process for integrating hemispherical grain silicon and a nitride-oxide capacitor dielectric layer for a dynamic random access memory capacitor structure | Jung-Ho Chang, Hsi-Chuan Chen | 2001-02-27 |
| 6165830 | Method to decrease capacitance depletion, for a DRAM capacitor, via selective deposition of a doped polysilicon layer on a selectively formed hemispherical grain silicon layer | Jung-Ho Chang, Hsi-Chuan Chen | 2000-12-26 |
| 6162732 | Method for reducing capacitance depletion during hemispherical grain polysilicon synthesis for DRAM | Chingfu Lin | 2000-12-19 |
| 6130146 | In-situ nitride and oxynitride deposition process in the same chamber | Jung-Ho Chang, Hsi-Chuan Chen | 2000-10-10 |
| 6127221 | In situ, one step, formation of selective hemispherical grain silicon layer, and a nitride-oxide dielectric capacitor layer, for a DRAM application | Jung-Ho Chang, Hsi-Chuan Chen | 2000-10-03 |
| 6100136 | Method of fabricating capacitor capable of maintaining the height of the peripheral area of the capacitor | Chih-Hsing Yu | 2000-08-08 |
| 6074931 | Process for recess-free planarization of shallow trench isolation | Jung-Ho Chang, Hsi-Chuan Chen | 2000-06-13 |
| 6046083 | Growth enhancement of hemispherical grain silicon on a doped polysilicon storage node capacitor structure, for dynamic random access memory applications | Jung-Ho Chang, Hsi-Chuan Chen, Kuo-Shu Tseng | 2000-04-04 |
| 6037238 | Process to reduce defect formation occurring during shallow trench isolation formation | Jung-Ho Chang, Hsi-Chuan Chen | 2000-03-14 |
| 6037219 | One step in situ doped amorphous silicon layers used for selective hemispherical grain silicon formation for crown shaped capacitor applications | Jung-Ho Chang, Hsi-Chuan Chen, Kuo-Shu Tseng | 2000-03-14 |
| 6004859 | Method for fabricating a stack capacitor | — | 1999-12-21 |
| 5930625 | Method for fabricating a stacked, or crown shaped, capacitor structure | Jung-Ho Chang, Hsi-Chuan Chen | 1999-07-27 |
| 5913119 | Method of selective growth of a hemispherical grain silicon layer on the outer sides of a crown shaped DRAM capacitor structure | Jung-Ho Chang, Hsi-Chuan Chen | 1999-06-15 |
| 5897352 | Method of manufacturing hemispherical grained polysilicon with improved adhesion and reduced capacitance depletion | Jung-Ho Chang, Hsi-Chuan Chen | 1999-04-27 |
| 5877052 | Resolution of hemispherical grained silicon peeling and row-disturb problems for dynamic random access memory, stacked capacitor structures | Jung-Ho Chang, Hsi-Chuan Chen, Kuo-Shu Tseng | 1999-03-02 |