Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7917881 | Timing of a circuit design | Hsi-Chuan Chen, Chung-Do Yang, Jeong-Tyng Li | 2011-03-29 |
| 7739630 | Optimizing a circuit design | Hsi-Chuan Chen, Chung-Do Yang, Jeong-Tyng Li | 2010-06-15 |
| 6618846 | Estimating capacitance effects in integrated circuits using congestion estimations | — | 2003-09-09 |
| 5847965 | Method for automatic iterative area placement of module cells in an integrated circuit layout | — | 1998-12-08 |
| 5798936 | Congestion-driven placement method and computer-implemented integrated-circuit design tool | — | 1998-08-25 |