Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11144690 | Extensible layer mapping for in-design verification | Jun Wang, Yun-Jui Li, Bin Xu, Cheng-Ming Wu, Yu Fan Lu +4 more | 2021-10-12 |
| 7917881 | Timing of a circuit design | Hsi-Chuan Chen, Chih-Liang Cheng, Chung-Do Yang | 2011-03-29 |
| 7739630 | Optimizing a circuit design | Hsi-Chuan Chen, Chih-Liang Cheng, Chung-Do Yang | 2010-06-15 |
| 5835751 | Structure and method for providing reconfigurable emulation circuit | Nang-Ping Chen, Robert J. Ko, Thomas B. Huang, Ming Yang Wang | 1998-11-10 |
| 5649167 | Methods for controlling timing in a logic emulation system | Nang-Ping Chen, Robert J. Ko, Thomas B. Huang, Ming Yang Wang | 1997-07-15 |
| 5475830 | Structure and method for providing a reconfigurable emulation circuit without hold time violations | Nang-Ping Chen, Robert J. Ko, Thomas B. Huang, Ming Yang Wang | 1995-12-12 |
| 5425036 | Method and apparatus for debugging reconfigurable emulation systems | Dick Liu, Thomas B. Huang, Kenneth S. K. Choi | 1995-06-13 |