Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7082587 | Method of estimating path delays in an IC | Pinhong Chen | 2006-07-25 |
| 7051310 | Two-stage clock tree synthesis with buffer distribution balancing | Chung-wen Tsao | 2006-05-23 |
| 6925619 | IC conductor capacitance estimation method | Eddy Pramono | 2005-08-02 |
| 6782519 | Clock tree synthesis for mixed domain clocks | Jui-Ming Chang, Wei-Jin Dai | 2004-08-24 |
| 6763513 | Clock tree synthesizer for balancing reconvergent and crossover clock trees | Jui-Ming Chang | 2004-07-13 |
| 6751786 | Clock tree synthesis for a hierarchically partitioned IC layout | Wei-Jin Dai | 2004-06-15 |
| 6351840 | Method for balancing a clock tree | — | 2002-02-26 |