CT

Chung-wen Tsao

CS Cadence Design Systems: 1 patents #1,216 of 2,263Top 55%
📍 San Jose, CA: #22,480 of 32,062 inventorsTop 75%
🗺 California: #247,236 of 386,348 inventorsTop 65%
Overall (All Time): #3,417,898 of 4,157,543Top 85%
1
Patents All Time

Issued Patents All Time

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
7051310 Two-stage clock tree synthesis with buffer distribution balancing Chin-Chi Teng 2006-05-23