Issued Patents All Time
Showing 1–25 of 49 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12340158 | Circuit synthesis optimization for implements on integrated circuit | Chao-Chun Lo, Boh-Yi Huang, Chih-yuan Stephen Yu, Chih-Sheng Hou | 2025-06-24 |
| 12321682 | Post-routing congestion optimization | Ching-Hsiang Hsu, Heng-Yi Lin | 2025-06-03 |
| 12299376 | Hard-to-fix (HTF) design rule check (DRC) violations prediction | Ching-Hsiang Hsu, Shih-Yao Lin | 2025-05-13 |
| 12242788 | Method and system for generating layout design of integrated circuit | Shih-Yao Lin, Yin-An Chen, Shih Feng Hong | 2025-03-04 |
| 12216980 | Method and system for fixing violation of layout | Song Liu, Pei-Pei Chen, Heng-Yi Lin, Shih-Yao Lin, Chin-Hsien Wang | 2025-02-04 |
| 12154851 | Method of forming a semiconductor device with inter-layer vias | Ching-Fang Chen, Jia-Jye Shen | 2024-11-26 |
| 12106034 | Rule check violation prediction systems and methods | Henry Lin, Szu-Ju Huang, Yin-An Chen, Amos Hong | 2024-10-01 |
| 12099793 | Rule check violation prediction systems and methods | Henry Lin, Szu-Ju Huang, Yin-An Chen, Amos Hong | 2024-09-24 |
| 12039249 | System and method for diagnosing design rule check violations | Yu-Chen Huang, Heng-Yi Lin | 2024-07-16 |
| 12039251 | Cell layout of semiconductor device | Huang-Yu Chen, Yun-Han Lee | 2024-07-16 |
| 12019971 | Static voltage drop (SIR) violation prediction systems and methods | Szu-Ju Huang, Shih-Yao Lin, Shih Feng Hung, Yin-An Chen | 2024-06-25 |
| 11928415 | Hard-to-fix (HTF) design rule check (DRC) violations prediction | Ching-Hsiang Hsu, Shih-Yao Lin | 2024-03-12 |
| 11900037 | Circuit synthesis optimization for implements on integrated circuit | Chao-Chun Lo, Boh-Yi Huang, Chih-yuan Stephen Yu, Chih-Sheng Hou | 2024-02-13 |
| 11893334 | Method for optimizing floor plan for an integrated circuit | Shi-Wen TAN, Song Liu, Shih-Yao Lin, Wen-Yuan FANG | 2024-02-06 |
| 11853675 | Method for optimizing floor plan for an integrated circuit | Shi-Wen TAN, Song Liu, Shih-Yao Lin, Wen-Yuan FANG | 2023-12-26 |
| 11853681 | Post-routing congestion optimization | Ching-Hsiang Hsu, Heng-Yi Lin | 2023-12-26 |
| 11816417 | Rule check violation prediction systems and methods | Henry Lin, Szu-Ju Huang, Yin-An Chen, Amos Hong | 2023-11-14 |
| 11709987 | Method and system for generating layout design of integrated circuit | Shih-Yao Lin, Yin-An Chen, Shih Feng Hong | 2023-07-25 |
| 11604917 | Static voltage drop (SIR) violation prediction systems and methods | Henry Lin, Szu-Ju Huang, Yin-An Chen, Amos Hong | 2023-03-14 |
| 11568119 | Cell layout of semiconductor device | Huang-Yu Chen, Yun-Han Lee | 2023-01-31 |
| 11562118 | Hard-to-fix (HTF) design rule check (DRC) violations prediction | Ching-Hsiang Hsu, Shih-Yao Lin | 2023-01-24 |
| 11481536 | Method and system for fixing violation of layout | Song Liu, Pei-Pei Chen, Heng-Yi Lin, Shih-Yao Lin, Chin-Hsien Wang | 2022-10-25 |
| 11443097 | System and method for diagnosing design rule check violations | Yu-Chen Huang, Heng-Yi Lin | 2022-09-13 |
| 11443096 | Method for optimizing floor plan for an integrated circuit | Shi-Wen TAN, Song Liu, Shih-Yao Lin, Wen-Yuan FANG | 2022-09-13 |
| 11347920 | Circuit synthesis optimization for implements on integrated circuit | Chao-Chun Lo, Boh-Yi Huang, Chih-yuan Stephen Yu, Chih-Sheng Hou | 2022-05-31 |