Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12340158 | Circuit synthesis optimization for implements on integrated circuit | Chao-Chun Lo, Boh-Yi Huang, Yi-Lin Chuang, Chih-Sheng Hou | 2025-06-24 |
| 12175175 | Systems and methods for generating synthesizable netlists from register transfer level designs | Boh-Yi Huang, Chao-Chun Lo, Tze-Chiang Huang, Chen-jih Lui | 2024-12-24 |
| 12169671 | Apparatus and method for mapping foundational components during design porting from one process technology to another process technology | Boh-Yi Huang, Chao-Chun Lo, Xiang Guo | 2024-12-17 |
| 11900035 | Attribute-point-based timing constraint formal verification | Chao-Chun Lo, Boh-Yi Huang | 2024-02-13 |
| 11900037 | Circuit synthesis optimization for implements on integrated circuit | Chao-Chun Lo, Boh-Yi Huang, Yi-Lin Chuang, Chih-Sheng Hou | 2024-02-13 |
| 11783104 | Apparatus and method for mapping foundational components during design porting from one process technology to another process technology | Boh-Yi Huang, Chao-Chun Lo, Xiang Guo | 2023-10-10 |
| 11620423 | Attribute-point-based timing constraint formal verification | Chao-Chun Lo, Boh-Yi Huang | 2023-04-04 |
| 11403448 | Apparatus and method for mapping foundational components during design porting from one process technology to another process technology | Boh-Yi Huang, Chao-Chun Lo, Xiang Guo | 2022-08-02 |
| 11347920 | Circuit synthesis optimization for implements on integrated circuit | Chao-Chun Lo, Boh-Yi Huang, Yi-Lin Chuang, Chih-Sheng Hou | 2022-05-31 |
| 10540462 | Method and apparatus for speeding up gate-level simulation | Wenyuan Lee, Boh-Yi Huang, Brent Lui, Tze-Chiang Huang | 2020-01-21 |
| 7925380 | Integrated transportation control for wafer fabrication facility | Ren You, Ming-I Wang | 2011-04-12 |
| 7684888 | Extendable MES for Cross-AMHS Transportation | Hsieh-Chi Chen | 2010-03-23 |