Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12340158 | Circuit synthesis optimization for implements on integrated circuit | Boh-Yi Huang, Chih-yuan Stephen Yu, Yi-Lin Chuang, Chih-Sheng Hou | 2025-06-24 |
| 12175175 | Systems and methods for generating synthesizable netlists from register transfer level designs | Boh-Yi Huang, Chih-yuan Stephen Yu, Tze-Chiang Huang, Chen-jih Lui | 2024-12-24 |
| 12169671 | Apparatus and method for mapping foundational components during design porting from one process technology to another process technology | Chih-yuan Stephen Yu, Boh-Yi Huang, Xiang Guo | 2024-12-17 |
| 11900035 | Attribute-point-based timing constraint formal verification | Boh-Yi Huang, Chih-yuan Stephen Yu | 2024-02-13 |
| 11900037 | Circuit synthesis optimization for implements on integrated circuit | Boh-Yi Huang, Chih-yuan Stephen Yu, Yi-Lin Chuang, Chih-Sheng Hou | 2024-02-13 |
| 11783104 | Apparatus and method for mapping foundational components during design porting from one process technology to another process technology | Chih-yuan Stephen Yu, Boh-Yi Huang, Xiang Guo | 2023-10-10 |
| 11620423 | Attribute-point-based timing constraint formal verification | Boh-Yi Huang, Chih-yuan Stephen Yu | 2023-04-04 |
| 11403448 | Apparatus and method for mapping foundational components during design porting from one process technology to another process technology | Chih-yuan Stephen Yu, Boh-Yi Huang, Xiang Guo | 2022-08-02 |
| 11347920 | Circuit synthesis optimization for implements on integrated circuit | Boh-Yi Huang, Chih-yuan Stephen Yu, Yi-Lin Chuang, Chih-Sheng Hou | 2022-05-31 |