Issued Patents All Time
Showing 1–25 of 56 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12367333 | Automated system and method for circuit design | Shin-Chi Chen, King-Ho Tam, Yu-Ze Lin | 2025-07-22 |
| 12346285 | Diagonal torus network | Jerry Chang Jui Kao, Yung-Chen Chien, Tzu-Ying Lin, Wei-Hsiang Ma, Chung-Hsing Wang | 2025-07-01 |
| 12336295 | Integrated circuit device and method | Wei-Ren Chen, Cheng-Yu Lin, Hui-Zhong Zhuang, Yung-Chen Chien, Jerry Chang Jui Kao +1 more | 2025-06-17 |
| 12039251 | Cell layout of semiconductor device | Yi-Lin Chuang, Yun-Han Lee | 2024-07-16 |
| 12013643 | Method of cutting conductive patterns | Chin-Hsiung Hsu, Tsong-Hua Ou, Wen-Hao Chen | 2024-06-18 |
| 12001773 | Automated system and method for circuit design | Shin-Chi Chen, King-Ho Tam, Yu-Ze Lin | 2024-06-04 |
| 11907007 | Clock signal distribution system, integrated circuit device and method | Jerry Chang Jui Kao, Sheng-Hsiung Chen, Jack Liu, Yung-Chen Chien, Wei-Hsiang Ma +1 more | 2024-02-20 |
| 11861284 | Conductor scheme selection and track planning for mixed-diagonal-manhattan routing | Sheng-Hsiung Chen, Chung-Hsing Wang, Jerry Chang Jui Kao | 2024-01-02 |
| 11715733 | Integrated circuit device and method | Wei-Ren Chen, Cheng-Yu Lin, Hui-Zhong Zhuang, Yung-Chen Chien, Jerry Chang Jui Kao +1 more | 2023-08-01 |
| 11669669 | Circuit layouts and related methods | Chin-Shen Lin, Wan-Yu Lo, Shao-Huan Wang, Kuo-Nan Yang, Chung-Hsing Wang +1 more | 2023-06-06 |
| 11620426 | Automated system and method for circuit design | Shin-Chi Chen, King-Ho Tam, Yu-Ze Lin | 2023-04-04 |
| 11568119 | Cell layout of semiconductor device | Yi-Lin Chuang, Yun-Han Lee | 2023-01-31 |
| 11501052 | Conductor scheme selection and track planning for mixed-diagonal-Manhattan routing | Sheng-Hsiung Chen, Chung-Hsing Wang, Jerry Chang Jui Kao | 2022-11-15 |
| 11429028 | Method of cutting conductive patterns | Chin-Hsiung Hsu, Tsong-Hua Ou, Wen-Hao Chen | 2022-08-30 |
| 11200364 | Method and associated system for circuit design | Chia-Cheng Chen, Ching-Fang Chen, Jen Ping Hsu | 2021-12-14 |
| 10922466 | Cell layout of semiconductor device | Yi-Lin Chuang, Yun-Han Lee | 2021-02-16 |
| 10509322 | Method of cutting conductive patterns | Chin-Hsiung Hsu, Tsong-Hua Ou, Wen-Hao Chen | 2019-12-17 |
| 10162925 | Cell layout of semiconductor device | Yi-Lin Chuang, Yun-Han Lee | 2018-12-25 |
| 9893009 | Duplicate layering and routing | Chi-Yeh Yu, Chung-Hsing Wang | 2018-02-13 |
| 9754073 | Layout optimization for integrated circuit design | Yuan-Te Hou, Yu-Hsiang Kao, Ken-Hsien Hsieh, Ru-Gun Liu, Lee-Chung Lu | 2017-09-05 |
| 9747402 | Methods for double-patterning-compliant standard cell design | Yuan-Te Hou, Fung Song Lee, Wen-Ju Yang, Gwan Sin Chang, Yi-Kan Cheng +2 more | 2017-08-29 |
| 9640450 | Method for reducing light-induced-degradation in manufacturing solar cell | Kuang-Yang Kuo, Wei-Lun LU, Chien-Chun Wang, Yu-Pan Pai | 2017-05-02 |
| 9594866 | Method for checking and fixing double-patterning layout | Dio Wang, Ken-Hsien Hsieh, Li-Chun Tien, Ru-Gun Liu, Lee-Chung Lu | 2017-03-14 |
| 9471742 | Method for displaying timing information of an integrated circuit floorplan in real time | Yi-Lin Chuang, Yun-Han Lee | 2016-10-18 |
| 9418196 | Layout optimization for integrated circuit design | Yuan-Te Hou, Yu-Hsiang Kao, Ken-Hsien Hsieh, Ru-Gun Liu, Lee-Chung Lu | 2016-08-16 |