Issued Patents All Time
Showing 26–50 of 56 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9384307 | Stitch and trim methods for double patterning compliant standard cell design | Chin-Hsiung Hsu, Chung-Hsing Wang | 2016-07-05 |
| 9380709 | Method of cutting conductive patterns | Chin-Hsiung Hsu, Tsong-Hua Ou, Wen-Hao Chen | 2016-06-28 |
| 9355202 | Promoting efficient cell usage to boost QoR in automated design | Ya Chen Wang, Tan-Li Chou | 2016-05-31 |
| 9317650 | Double patterning technology (DPT) layout routing | Fang-Yu Fan, Yuan-Te Hou, Wen-Hao Chen, Chung-Hsing Wang, Yi-Kan Cheng | 2016-04-19 |
| 9292645 | Layout optimization for integrated circuit design | Yuan-Te Hou, Yu-Hsiang Kao, Ken-Hsien Hsieh, Ru-Gun Liu, Lee-Chung Lu | 2016-03-22 |
| 9262577 | Layout method and system for multi-patterning integrated circuits | Tsong-Hua Ou, Ken-Hsien Hsieh, Chin-Hsiung Hsu | 2016-02-16 |
| 9213795 | Multiple via connections using connectivity rings | Chin-Hsiung Hsu, Li-Chun Tien, Lee-Chung Lu, Hui-Zhong Zhuang, Cheng-I Huang +2 more | 2015-12-15 |
| 9026953 | Compression method and system for use with multi-patterning | Chin-Hsiung Hsu, Wen-Hao Chen, Chung-Hsing Wang | 2015-05-05 |
| 8977991 | Method and system for replacing a pattern in a layout | Yuan-Te Hou, Chung-Min Fu, Chung-Hsing Wang, Wen-Hao Chen, Yi-Kan Cheng | 2015-03-10 |
| 8914755 | Layout re-decomposition for multiple patterning layouts | Chin-Hsiung Hsu, Yuan-Te Hou, Yen-Pin Chen, Wen-Hao Chen, Chung-Hsing Wang | 2014-12-16 |
| 8907441 | Methods for double-patterning-compliant standard cell design | Yuan-Te Hou, Fung Song Lee, Wen-Ju Yang, Gwan Sin Chang, Yi-Kan Cheng +2 more | 2014-12-09 |
| 8898600 | Layout optimization for integrated design | Yuan-Te Hou, Yu-Hsiang Kao, Ken-Hsien Hsieh, Ru-Gun Liu, Lee-Chung Lu | 2014-11-25 |
| 8898608 | Method for displaying timing information of an integrated circuit floorplan | Yi-Lin Chuang, Yun-Han Lee | 2014-11-25 |
| 8875067 | Reusable cut mask for multiple layers | Chin-Hsiung Hsu, Yuan-Te Hou, Wen-Hao Chen | 2014-10-28 |
| 8850368 | Double patterning technology (DPT) layout routing | Fang-Yu Fan, Yuan-Te Hou, Wen-Hao Chen, Chung-Hsing Wang, Yi-Kan Cheng | 2014-09-30 |
| 8813016 | Multiple via connections using connectivity rings | Chin-Hsiung Hsu, Li-Chun Tien, Lee-Chung Lu, Hui-Zhong Zhuang, Cheng-I Huang +2 more | 2014-08-19 |
| 8799834 | Self-aligned multiple patterning layout design | Li-Chun Tien, Ken-Hsien Hsieh, Jhih-Jian Wang, Chin-Chang Hsu, Chin-Hsiung Hsu +3 more | 2014-08-05 |
| 8745556 | Layout method and system for multi-patterning integrated circuits | Tsong-Hua Ou, Ken-Hsien Hsieh, Chin-Hsiung Hsu | 2014-06-03 |
| 8694945 | Automatic place and route method for electromigration tolerant power distribution | Chung-Hsing Wang, King-Ho Tam | 2014-04-08 |
| 8683392 | Double patterning methodology | Ken-Hsien Hsieh, Jhih-Jian Wang, Cheng Kun Tsai, Tsong-Hua Ou, Wen-Chun Huang +1 more | 2014-03-25 |
| 8601408 | Method and system for replacing a pattern in a layout | Yuan-Te Hou, Chung-Min Fu, Chung-Hsing Wang, Wen-Hao Chen, Yi-Kan Cheng | 2013-12-03 |
| 8601409 | Compression method and system for use with multi-patterning | Chin-Hsiung Hsu, Wen-Hao Chen, Chung-Hsing Wang | 2013-12-03 |
| 8584052 | Cell layout for multiple patterning technology | Yuan-Te Hou, Ken-Hsien Hsieh, Ru-Gun Liu, Lee-Chung Lu | 2013-11-12 |
| 8539396 | Stitch and trim methods for double patterning compliant standard cell design | Chin-Hsiung Hsu, Chung-Hsing Wang | 2013-09-17 |
| 8453095 | Systems and methods for creating frequency-dependent netlist | Ke-Ying Su, Ching-Shun Yang, Jui-Feng Kuan, Hsiao-Shu Chao, Yi-Kan Cheng +1 more | 2013-05-28 |