Issued Patents All Time
Showing 51–56 of 56 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8448100 | Tool and method for eliminating multi-patterning conflicts | Hung-Lung Lin, Chin-Chang Hsu, Ying-Yu Shen, Wen-Ju Yang, Hsiao-Shu Chao +5 more | 2013-05-21 |
| 8418111 | Method and apparatus for achieving multiple patterning technology compliant design layout | Fang-Yu Fan, Yuan-Te Hou, Lee-Chung Lu, Ru-Gun Liu, Ken-Hsien Hsieh +3 more | 2013-04-09 |
| 8418117 | Chip-level ECO shrink | Ho Che Yu, Chung-Hsing Wang, Hsiao-Shu Chao, Yi-Kan Cheng, Lee-Chung Lu | 2013-04-09 |
| 8365102 | Method for checking and fixing double-patterning layout | Dio Wang, Ken-Hsien Hsieh, Li-Chun Tien, Ru-Gun Liu, Lee-Chung Lu | 2013-01-29 |
| 8239806 | Routing system and method for double patterning technology | Yuan-Te Hou, Gwan Sin Chang, Wen-Ju Yang, Zhe-Wei Jiang, Yi-Kan Cheng +1 more | 2012-08-07 |
| 8211807 | Double patterning technology using single-patterning-spacer-technique | Ken-Hsien Hsieh, Tsong-Hua Ou, Fang-Yu Fan, Yuan-Te Hou, Ming-Feng Shieh +2 more | 2012-07-03 |