Issued Patents All Time
Showing 1–25 of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9768119 | Apparatus and method for mitigating dynamic IR voltage drop and electromigration affects | Chih-Yeh Yu, Yuan-Te Hou, Wen-Hao Chen, Wan-Yu Lo | 2017-09-19 |
| 9639647 | Method of making semiconductor device and system for performing the same | Wan-Yu Lo, Chin-Chou Liu, Huan Chi Tseng | 2017-05-02 |
| 9582633 | 3D device modeling for FinFET devices | Meng-Fu You, Po-Hsiang Huang, Wen-Hao Cheng | 2017-02-28 |
| 9367655 | Topography-aware lithography pattern check | I-Chang Shih, Ying-Chou Cheng, Yung-Fong Lu, Feng-Yuan Chiu, Chiu Hsiu Chen | 2016-06-14 |
| 9324178 | Three-dimensional semiconductor image reconstruction apparatus and method | Wen-Hao Cheng, Chih-Chiang Tu, Ajay Nandoriya | 2016-04-26 |
| 9318504 | Density gradient cell array | Yu-Jung Chang, C. R. Hsu, Chin-Chang Hsu, Wen-Ju Yang | 2016-04-19 |
| 9311440 | System and method of electromigration avoidance for automatic place-and-route | Jerry Chang Jui Kao, King-Ho Tam, Meng-Xiang Lee, Li-Chung Hsu, Chi-Yeh Yu +1 more | 2016-04-12 |
| 9262568 | Dummy pattern performance aware analysis and implementation | Meng-Fu You | 2016-02-16 |
| 9245073 | Pattern density-dependent mismatch modeling flow | Wan-Yu Lo, Shih-Cheng Yang, Chung-Kai Lin, Yung-Chow Peng | 2016-01-26 |
| 9223919 | System and method of electromigration mitigation in stacked IC designs | Chi-Yeh Yu, Ping-Heng Yeh | 2015-12-29 |
| 9147694 | Density gradient cell array | Yu-Jung Chang, C. R. Hsu, Chin-Chang Hsu, Wen-Ju Yang | 2015-09-29 |
| 9141745 | Method and system for designing Fin-FET semiconductor device | Yung-Fong Lu, Chung-Hsing Wang | 2015-09-22 |
| 9122836 | Recognition of template patterns with mask information | Yung-Fong Lu, Wen-Ju Yang, Chin-Chang Hsu | 2015-09-01 |
| 8977991 | Method and system for replacing a pattern in a layout | Huang-Yu Chen, Yuan-Te Hou, Chung-Hsing Wang, Wen-Hao Chen, Yi-Kan Cheng | 2015-03-10 |
| 8978003 | Method of making semiconductor device and a control system for performing the same | Wan-Yu Lo, Chin-Chou Liu, Huan Chi Tseng | 2015-03-10 |
| 8901492 | Three-dimensional semiconductor image reconstruction apparatus and method | Wen-Hao Cheng, Ajay Nandoriya, Chih-Chiang Tu | 2014-12-02 |
| 8786094 | Semiconductor devices and methods of manufacture thereof | Wen-Hao Chen, Dian-Hau Chen | 2014-07-22 |
| 8782593 | Thermal analysis of integrated circuit packages | Wan-Yu Lo, Meng-Fu You, Po-Hsiang Huang, Cheng-Chieh Hsieh | 2014-07-15 |
| 8726208 | DFM improvement utility with unified interface | Wen-Hao Chen, Zhe-Wei Jiang | 2014-05-13 |
| 8726200 | Recognition of template patterns with mask information | Yung-Fong Lu, Wen-Ju Yang, Chin-Chang Hsu | 2014-05-13 |
| 8701073 | System and method for across-chip thermal and power management in stacked IC designs | William Wu Shen, Po-Hsiang Huang, Meng-Fu You, Chi-Yeh Yu | 2014-04-15 |
| 8677292 | Cell-context aware integrated circuit design | Yen-Pin Chen, Yung-Fong Lu | 2014-03-18 |
| 8631372 | System and method of electromigration mitigation in stacked IC designs | Chi-Yeh Yu, Ping-Heng Yeh | 2014-01-14 |
| 8601408 | Method and system for replacing a pattern in a layout | Huang-Yu Chen, Yuan-Te Hou, Chung-Hsing Wang, Wen-Hao Chen, Yi-Kan Cheng | 2013-12-03 |
| 8577717 | Method and system for predicting shrinkable yield for business assessment of integrated circuit design shrink | Yu-Chyi Harn | 2013-11-05 |