Issued Patents All Time
Showing 1–25 of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12299371 | Dummy cells placed adjacent functional blocks | Wei Hu, Shih-Hsuan Chien, You-Cheng Xiao, Ya-Chi Chou | 2025-05-13 |
| 12243821 | Conductive line structures and method of forming same | Hiranmay Biswas, Kuo-Nan Yang, Chung-Hsing Wang, Stefan Rusu, Chin-Shen Lin | 2025-03-04 |
| 11941338 | Integrated circuit with dummy boundary cells | Wei Hu, Chih-Ming Chao | 2024-03-26 |
| 11935833 | Method of forming power grid structures | Hiranmay Biswas, Kuo-Nan Yang, Chung-Hsing Wang, Stefan Rusu, Chin-Shen Lin | 2024-03-19 |
| 11443094 | Method of inserting dummy boundary cells for macro/IP and IC | Wei Hu, Chih-Ming Chao | 2022-09-13 |
| 11251124 | Power grid structures and method of forming the same | Hiranmay Biswas, Chung-Hsing Wang, Kuo-Nan Yang, Stefan Rusu, Chin-Shen Lin | 2022-02-15 |
| 11088092 | Via rail solution for high power electromigration | Kam-Tou Sio, Chih-Ming Lai, Chun-Kuang Chen, Chih-Liang Chen, Charles Chew-Yuen Young +3 more | 2021-08-10 |
| 11063005 | Via rail solution for high power electromigration | Kam-Tou Sio, Chih-Ming Lai, Chun-Kuang Chen, Chih-Liang Chen, Charles Chew-Yuen Young +3 more | 2021-07-13 |
| 10861790 | Power strap structure for high performance and low current density | Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kam-Tou Sio +6 more | 2020-12-08 |
| 10510688 | Via rail solution for high power electromigration | Kam-Tou Sio, Chih-Ming Lai, Chun-Kuang Chen, Chih-Liang Chen, Charles Chew-Yuen Young +3 more | 2019-12-17 |
| 10170422 | Power strap structure for high performance and low current density | Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kam-Tou Sio +6 more | 2019-01-01 |
| 9911697 | Power strap structure for high performance and low current density | Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kam-Tou Sio +6 more | 2018-03-06 |
| 9900005 | Switch cell structure and method | Chih-Liang Chen, Ho Che Yu | 2018-02-20 |
| 9893009 | Duplicate layering and routing | Huang-Yu Chen, Chung-Hsing Wang | 2018-02-13 |
| 9619599 | System for and method of checking joule heating of an integrated circuit design | Ming-Hsien Lin, Wen-Hao Chen | 2017-04-11 |
| 9405883 | Power rail for preventing DC electromigration | Chin-Shen Lin, Jerry Chang Jui Kao, Nitesh Katta, Chou-Kun Lin, Yi-Chuin Tsai +1 more | 2016-08-02 |
| 9311440 | System and method of electromigration avoidance for automatic place-and-route | Jerry Chang Jui Kao, King-Ho Tam, Meng-Xiang Lee, Li-Chung Hsu, Chung-Min Fu +1 more | 2016-04-12 |
| 9223919 | System and method of electromigration mitigation in stacked IC designs | Chung-Min Fu, Ping-Heng Yeh | 2015-12-29 |
| 9214390 | Method for forming through-silicon via (TSV) with diffused isolation well | — | 2015-12-15 |
| 9165882 | Power rail for preventing DC electromigration | Chin-Shen Lin, Jerry Chang Jui Kao, Nitesh Katta, Chou-Kun Lin, Yi-Chuin Tsai +1 more | 2015-10-20 |
| 9064081 | Generating database for cells routable in pin layer | Meng-Kai Hsu, Yuan-Te Hou, Wen-Hao Chen | 2015-06-23 |
| 8766409 | Method and structure for through-silicon via (TSV) with diffused isolation well | — | 2014-07-01 |
| 8701073 | System and method for across-chip thermal and power management in stacked IC designs | Chung-Min Fu, William Wu Shen, Po-Hsiang Huang, Meng-Fu You | 2014-04-15 |
| 8680882 | 3D-IC interposer testing structure and method of testing the structure | Nan-Hsin Tseng | 2014-03-25 |
| 8631372 | System and method of electromigration mitigation in stacked IC designs | Chung-Min Fu, Ping-Heng Yeh | 2014-01-14 |