Issued Patents All Time
Showing 1–25 of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12433032 | Semiconductor structure including boundary header cell and method for manufacturing the same | Hao-Tien Kan, Yan You, Kuo-Nan Yang, Chung-Hsing Wang | 2025-09-30 |
| 12380265 | Integrated circuit and method of forming the same | John Lin, Kuo-Nan Yang, Chung-Hsing Wang | 2025-08-05 |
| 12243821 | Conductive line structures and method of forming same | Hiranmay Biswas, Chi-Yeh Yu, Kuo-Nan Yang, Chung-Hsing Wang, Stefan Rusu | 2025-03-04 |
| 12191248 | Semiconductor arrangement and method of making | Wan-Yu Lo, Chung-Hsing Wang, Kuo-Nan Yang, Hsiang-Ku Shen, Dian-Hau Chen | 2025-01-07 |
| 12182488 | Semiconductor device including standard-cell-adapted power grid arrangement | Hiranmay Biswas, Chung-Hsing Wang, Kuo-Nan Yang | 2024-12-31 |
| 12176288 | Semiconductor device including frontside power mesh and backside power mesh and manufacturing method thereof | Wan-Yu Lo, Chi-Yu Lu, Kuo-Nan Yang, Chih-Liang Chen, Chung-Hsing Wang | 2024-12-24 |
| 12107048 | Layouts for conductive layers in integrated circuits | Wan-Yu Lo, Chung-Hsing Wang, Kuo-Nan Yang, Meng-Xiang Lee, Hao-Tien Kan +1 more | 2024-10-01 |
| 12093625 | Integrated circuit design method, system and computer program product | Wan-Yu Lo, Kuo-Nan Yang, Chung-Hsing Wang | 2024-09-17 |
| 11943939 | Integrated circuit device and method | Meng-Kai Hsu, Jerry Chang Jui Kao, Ming-Tao Yu, Tzu-Ying Lin, Chung-Hsing Wang | 2024-03-26 |
| 11935833 | Method of forming power grid structures | Hiranmay Biswas, Chi-Yeh Yu, Kuo-Nan Yang, Chung-Hsing Wang, Stefan Rusu | 2024-03-19 |
| 11929331 | Routing structure | Wan-Yu Lo, Meng-Xiang Lee, Hao-Tien Kan, Kuo-Nan Yang, Chung-Hsing Wang | 2024-03-12 |
| 11809803 | Method for evaluating failure-in-time | Ming-Hsien Lin, Kuo-Nan Yang, Chung-Hsing Wang | 2023-11-07 |
| 11775725 | System and computer program product for integrated circuit design | Hiranmay Biswas, Kuo-Nan Yang, Chung-Hsing Wang | 2023-10-03 |
| 11727183 | Method of fabricating semiconductor device including standard-cell-adapted power grid arrangement | Hiranmay Biswas, Chung-Hsing Wang, Kuo-Nan Yang | 2023-08-15 |
| 11704469 | Integrated circuit and method of forming the same | John Lin, Kuo-Nan Yang, Chung-Hsing Wang | 2023-07-18 |
| 11669669 | Circuit layouts and related methods | Wan-Yu Lo, Shao-Huan Wang, Kuo-Nan Yang, Chung-Hsing Wang, Sheng-Hsiung Chen +1 more | 2023-06-06 |
| 11657199 | Method for analyzing electromigration (EM) in integrated circuit | Ming-Hsien Lin, Wan-Yu Lo, Meng-Xiang Lee | 2023-05-23 |
| 11600568 | Layouts for conductive layers in integrated circuits | Wan-Yu Lo, Chung-Hsing Wang, Kuo-Nan Yang, Meng-Xiang Lee, Hao-Tien Kan +1 more | 2023-03-07 |
| 11532562 | Routing structure and method of forming the same | Wan-Yu Lo, Meng-Xiang Lee, Hao-Tien Kan, Kuo-Nan Yang, Chung-Hsing Wang | 2022-12-20 |
| 11455448 | Method for analyzing electromigration (EM) in integrated circuit | Ming-Hsien Lin, Wan-Yu Lo, Meng-Xiang Lee | 2022-09-27 |
| 11366951 | Method for evaluating failure-in-time | Ming-Hsien Lin, Kuo-Nan Yang, Chung-Hsing Wang | 2022-06-21 |
| 11347922 | Method of fabricating semiconductor device including standard-cell-adapted power grid arrangement | Hiranmay Biswas, Chung-Hsing Wang, Kuo-Nan Yang | 2022-05-31 |
| 11251124 | Power grid structures and method of forming the same | Hiranmay Biswas, Chi-Yeh Yu, Chung-Hsing Wang, Kuo-Nan Yang, Stefan Rusu | 2022-02-15 |
| 11211327 | Via sizing for IR drop reduction | Hiranmay Biswas, Kuo-Nan Yang, Chung-Hsing Wang | 2021-12-28 |
| 11205032 | Integrated circuit design method, system and computer program product | Chung-Hsing Wang, Kuo-Nan Yang, Hiranmay Biswas | 2021-12-21 |