Issued Patents All Time
Showing 26–50 of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11182528 | Electromigration sign-off tool | Yu-Tseng Hsien, Ching-Shun Yang, Jui-Feng Kuan | 2021-11-23 |
| 11055470 | Optimized electromigration analysis | Ching-Shun Yang, Hsien Yu-Tseng | 2021-07-06 |
| 11017146 | Integrated circuit and method of forming the same | John Lin, Chung-Hsing Wang, Kuo-Nan Yang | 2021-05-25 |
| 10997347 | Integrated circuit design method, system and computer program product | Wan-Yu Lo, Chung-Hsing Wang, Kuo-Nan Yang | 2021-05-04 |
| 10963609 | Method for analyzing electromigration (EM) in integrated circuit | Ming-Hsien Lin, Wan-Yu Lo, Meng-Xiang Lee | 2021-03-30 |
| 10956647 | Method for evaluating failure-in-time | Ming-Hsien Lin, Kuo-Nan Yang, Chung-Hsing Wang | 2021-03-23 |
| 10943045 | Semiconductor device including standard-cell-adapted power grid arrangement and method for generating layout diagram of same | Hiranmay Biswas, Chung-Hsing Wang, Kuo-Nan Yang | 2021-03-09 |
| 10867916 | Via sizing for IR drop reduction | Hiranmay Biswas, Kuo-Nan Yang, Chung-Hsing Wang | 2020-12-15 |
| 10726174 | System and method for simulating reliability of circuit design | Meng-Xiang Lee, Kuo-Nan Yang, Chung-Hsing Wang | 2020-07-28 |
| 10719652 | Electromigration sign-off tool | Yu-Tseng Hsien, Ching-Shun Yang, Jui-Feng Kuan | 2020-07-21 |
| 10509886 | Method, system, and storage medium for RC extraction using hierarchical modeling architecture | Meng-Xiang Lee, Kuo-Nan Yang, Chung-Hsing Wang | 2019-12-17 |
| 10460070 | Optimized electromigration analysis | Ching-Shun Yang, Hsien Yu-Tseng | 2019-10-29 |
| 10346576 | Electromigration sign-off methodology | Yu-Tseng Hsien, Ching-Shun Yang, Jui-Feng Kuan | 2019-07-09 |
| 10157257 | Method for analyzing an electromigration (EM) rule violation in an integrated circuit | Wan-Yu Lo, Chung-Hsing Wang, Kuo-Nan Yang | 2018-12-18 |
| 10157258 | Method for evaluating failure-in-time | Ming-Hsien Lin, Kuo-Nan Yang, Chung-Hsing Wang | 2018-12-18 |
| 10042967 | Electromigration sign-off methodology | Yu-Tseng Hsien, Ching-Shun Yang, Jui-Feng Kuan | 2018-08-07 |
| 9852989 | Power grid of integrated circuit | Min-Yuan Tsai, Kuo-Nan Yang, Chung-Hsing Wang | 2017-12-26 |
| 9824968 | Method, system and computer readable medium using stitching for mask assignment of patterns | Hsien Yu-Tseng, Shih-Kai Lin, Yu Jiang, Heng-Kai Liu, Mu-Jen Huang +1 more | 2017-11-21 |
| 9564896 | Post-silicon tuning in voltage control of semiconductor integrated circuits | Jerry Chang Jui Kao, Chien-Ju Chao, Nitesh Katta, Kuo-Nan Yang, Chung-Hsing Wang | 2017-02-07 |
| 9509301 | Voltage control of semiconductor integrated circuits | Jerry Chang Jui Kao, Chien-Ju Chao, Chou-Kun Lin, King-Ho Tam, Kuo-Nan Yang +1 more | 2016-11-29 |
| 9501602 | Electromigration-aware layout generation | Nitesh Katta, Jerry Chang Jui Kao, Yi-Chuin Tsai, Chou-Kun Lin, Kuo-Nan Yang +1 more | 2016-11-22 |
| 9405883 | Power rail for preventing DC electromigration | Jerry Chang Jui Kao, Nitesh Katta, Chou-Kun Lin, Yi-Chuin Tsai, Chi-Yeh Yu +1 more | 2016-08-02 |
| 9367660 | Electromigration-aware layout generation | Nitesh Katta, Jerry Chang Jui Kao, Yi-Chuin Tsai, Chien-Ju Chao, Kuo-Nan Yang +1 more | 2016-06-14 |
| 9342646 | Method, system and computer readable medium using stitching for mask assignment of patterns | Hsien Yu-Tseng, Shih-Kai Lin, Yu Jiang, Heng-Kai Liu, Mu-Jen Huang +1 more | 2016-05-17 |
| 9165882 | Power rail for preventing DC electromigration | Jerry Chang Jui Kao, Nitesh Katta, Chou-Kun Lin, Yi-Chuin Tsai, Chi-Yeh Yu +1 more | 2015-10-20 |