Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12265774 | Boundary cell | Yu-Jung Chang, Wen-Ju Yang | 2025-04-01 |
| 12229489 | System and method of verifying slanted layout components | Yuan-Te Hou | 2025-02-18 |
| 12165969 | Integrated circuit device and method | Yu-Jung Chang, Nien-Yu Tsai, Wen-Ju Yang | 2024-12-10 |
| 11861288 | System and method of verifying slanted layout components | Yuan-Te Hou | 2024-01-02 |
| 11714947 | Method and layout of an integrated circuit | Mahantesh Hanchinal, Shu-Yi Ying, Chi Wei Hu | 2023-08-01 |
| 11709986 | Boundary cell | Yu-Jung Chang, Wen-Ju Yang | 2023-07-25 |
| 11341308 | Method and layout of an integrated circuit | Mahantesh Hanchinal, Shu-Yi Ying, Chi Wei Hu | 2022-05-24 |
| 11062074 | Boundary cell | Yu-Jung Chang, Wen-Ju Yang | 2021-07-13 |
| 10936780 | Method and layout of an integrated circuit | Mahantesh Hanchinal, Chi Wei Hu, Shu-Yi Ying | 2021-03-02 |
| 10402529 | Method and layout of an integrated circuit | Mahantesh Hanchinal, Chi Wei Hu, Shu-Yi Ying | 2019-09-03 |
| 9852989 | Power grid of integrated circuit | Chin-Shen Lin, Kuo-Nan Yang, Chung-Hsing Wang | 2017-12-26 |
| 9471744 | Triple-pattern lithography layout decomposition | Hung-Lung Lin, Chin-Chang Hsu, Wen-Ju Yang, Chien Lin Ho | 2016-10-18 |
| 9122838 | Triple-pattern lithography layout decomposition | Hung-Lung Lin, Chin-Chang Hsu, Wen-Ju Yang, Chien Lin Ho | 2015-09-01 |
| 8875065 | Triple-pattern lithography layout decomposition validation | Hung-Lung Lin, Chin-Chang Hsu, Wen-Ju Yang | 2014-10-28 |
| 8869090 | Stretch dummy cell insertion in FinFET process | Li Ke, Jia-Rong Hsu, Hung-Lung Lin, Wen-Ju Yang | 2014-10-21 |