Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12412019 | Method and system for latch-up prevention | Po-Chia Lai, Kuo-Ji Chen, Wen-Hao Chen, Wun-Jie Lin, Yu-Ti Su +4 more | 2025-09-09 |
| 11714947 | Method and layout of an integrated circuit | Mahantesh Hanchinal, Chi Wei Hu, Min-Yuan Tsai | 2023-08-01 |
| 11615227 | Method and system for latch-up prevention | Po-Chia Lai, Kuo-Ji Chen, Wen-Hao Chen, Wun-Jie Lin, Yu-Ti Su +4 more | 2023-03-28 |
| 11341308 | Method and layout of an integrated circuit | Mahantesh Hanchinal, Chi Wei Hu, Min-Yuan Tsai | 2022-05-24 |
| 11087063 | Method of generating layout diagram including dummy pattern conversion and system of generating same | Ritesh Kumar, Chung-Hsing Wang, Kuo-Nan Yang, Hiranmay Biswas | 2021-08-10 |
| 10936780 | Method and layout of an integrated circuit | Mahantesh Hanchinal, Chi Wei Hu, Min-Yuan Tsai | 2021-03-02 |
| 10872190 | Method and system for latch-up prevention | Po-Chia Lai, Kuo-Ji Chen, Wen-Hao Chen, Wun-Jie Lin, Yu-Ti Su +4 more | 2020-12-22 |
| 10402529 | Method and layout of an integrated circuit | Mahantesh Hanchinal, Chi Wei Hu, Min-Yuan Tsai | 2019-09-03 |
| 10331838 | Semiconductor device with fill cells | Jung-Chan Yang, Hui-Zhong Zhuang, Ting-Wei Chiang, Yun-Xiang Lin, Tien-Yu Kuo | 2019-06-25 |
| 9672315 | Optimization for circuit migration | Lee-Chung Lu, Yi-Kan Cheng, Chung-Hsing Wang, Chen-Fu Huang, Hsiao-Shu Chao +3 more | 2017-06-06 |
| 9275186 | Optimization for circuit migration | Lee-Chung Lu, Yi-Kan Cheng, Chung-Hsing Wang, Chen-Fu Huang, Hsiao-Shu Chao +3 more | 2016-03-01 |
| 8232824 | Clock circuit and method for pulsed latch circuits | Chung-Hsing Wang, Chih-Chieh Chen, Chih Sheng Tsai | 2012-07-31 |
| 7746142 | Circuit and method for clock skew compensation in voltage scaling | Wei-Pin Changchein, Fu-Lung Hsueh | 2010-06-29 |