Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12382725 | Variable-sized active regions for a semiconductor device and methods of making same | Ru-Yu WANG, Kao-Cheng Lin, Pin-Dai Sue, Ting-Wei Chiang | 2025-08-05 |
| 12328860 | Semiconductor device with increased unity density | Jhih-Siang HU, Ru-Yu WANG, Jung-Hsuan Chen, Ting-Wei Chiang | 2025-06-10 |
| 12299371 | Dummy cells placed adjacent functional blocks | Chi-Yeh Yu, Wei Hu, Shih-Hsuan Chien, Ya-Chi Chou | 2025-05-13 |
| 12167583 | Method of forming semiconductor device with increased unit density | Jhih-Siang HU, Ru-Yu WANG, Jung-Hsuan Chen, Ting-Wei Chiang | 2024-12-10 |
| 12048137 | Semiconductor arrangement and method of manufacture | Po-Sheng Wang, Ru-Yu WANG, Yangsyu Lin | 2024-07-23 |
| 11552085 | Semiconductor device including memory cell and fin arrangements | Jhih-Siang HU, Ru-Yu WANG, Jung-Hsuan Chen, Ting-Wei Chiang | 2023-01-10 |
| 9530727 | Conductive line routing for multi-patterning technology | Wei Min Chan, Ken-Hsien Hsieh | 2016-12-27 |
| 9425095 | Distributed metal routing | Yen-Huei Chen, Jung-Hsuan Chen, Shao-Yu Chou, Li-Chun Tien, Hung-Jen Liao | 2016-08-23 |
| 9041069 | Distributed metal routing | Yen-Huei Chen, Jung-Hsuan Chen, Shao-Yu Chou, Li-Chun Tien, Hung-Jen Liao | 2015-05-26 |
| 9029230 | Conductive line routing for multi-patterning technology | Wei Min Chan, Ken-Hsien Hsieh | 2015-05-12 |
| 8837250 | Method and apparatus for word line decoder layout | Hong-Chen Cheng, Chung-Ji Lu, Cheng Hung Lee, Jung-Hsuan Chen, Li-Chun Tien | 2014-09-16 |
| 8692333 | Semiconductor device for word line driver with efficient routing of conductor for decreased gate resistance | Yen-Huei Chen, Jung-Hsuan Chen, Shao-Yu Chou | 2014-04-08 |
| 8013770 | Decoder architecture with sub-thermometer codes for DACs | Robit Yang, Ying-Chi Hsu, Wen-Shen Chou | 2011-09-06 |